intel_de_write_fw(dev_priv, DSPOFFSET(i9xx_plane),
DISP_OFFSET_Y(y) | DISP_OFFSET_X(x));
} else if (DISPLAY_VER(dev_priv) >= 4) {
- intel_de_write_fw(dev_priv, DSPLINOFF(i9xx_plane),
+ intel_de_write_fw(dev_priv, DSPLINOFF(dev_priv, i9xx_plane),
linear_offset);
intel_de_write_fw(dev_priv, DSPTILEOFF(i9xx_plane),
DISP_OFFSET_Y(y) | DISP_OFFSET_X(x));
DSPTILEOFF(i9xx_plane));
else
offset = intel_de_read(dev_priv,
- DSPLINOFF(i9xx_plane));
+ DSPLINOFF(dev_priv, i9xx_plane));
base = intel_de_read(dev_priv, DSPSURF(i9xx_plane)) & DISP_ADDR_MASK;
} else {
offset = 0;
#define DSPADDR(dev_priv, plane) _MMIO_PIPE2(dev_priv, plane, _DSPAADDR)
#define _DSPALINOFF 0x70184 /* i965+ */
-#define DSPLINOFF(plane) _MMIO_PIPE2(dev_priv, plane, _DSPALINOFF)
+#define DSPLINOFF(dev_priv, plane) _MMIO_PIPE2(dev_priv, plane, _DSPALINOFF)
#define _DSPASTRIDE 0x70188
#define DSPSTRIDE(plane) _MMIO_PIPE2(dev_priv, plane, _DSPASTRIDE)