return retval;
 }
 
-bool ath9k_get_channel_edges(struct ath_hw *ah,
-                            u16 flags, u16 *low,
-                            u16 *high)
-{
-       struct ath9k_hw_capabilities *pCap = &ah->caps;
-
-       if (flags & CHANNEL_5GHZ) {
-               *low = pCap->low_5ghz_chan;
-               *high = pCap->high_5ghz_chan;
-               return true;
-       }
-       if ((flags & CHANNEL_2GHZ)) {
-               *low = pCap->low_2ghz_chan;
-               *high = pCap->high_2ghz_chan;
-               return true;
-       }
-       return false;
-}
-
 u16 ath9k_hw_computetxtime(struct ath_hw *ah,
                           u8 phy, int kbps,
                           u32 frameLen, u16 rateix,
        if (AR_SREV_9300_20_OR_LATER(ah))
                ah->misc_mode |= AR_PCU_ALWAYS_PERFORM_KEYSEARCH;
 
-       pCap->low_2ghz_chan = 2312;
-       pCap->high_2ghz_chan = 2732;
-
-       pCap->low_5ghz_chan = 4920;
-       pCap->high_5ghz_chan = 6100;
-
        common->crypt_caps |= ATH_CRYPT_CAP_CIPHER_AESCCM;
 
        if (ah->hw_version.devid != AR2427_DEVID_PCIE)
 
 
 struct ath9k_hw_capabilities {
        u32 hw_caps; /* ATH9K_HW_CAP_* from ath9k_hw_caps */
-       u16 low_5ghz_chan, high_5ghz_chan;
-       u16 low_2ghz_chan, high_2ghz_chan;
        u16 rts_aggr_limit;
        u8 tx_chainmask;
        u8 rx_chainmask;
 void ath9k_hw_write_array(struct ath_hw *ah, struct ar5416IniArray *array,
                          int column, unsigned int *writecnt);
 u32 ath9k_hw_reverse_bits(u32 val, u32 n);
-bool ath9k_get_channel_edges(struct ath_hw *ah, u16 flags, u16 *low, u16 *high);
 u16 ath9k_hw_computetxtime(struct ath_hw *ah,
                           u8 phy, int kbps,
                           u32 frameLen, u16 rateix, bool shortPreamble);