clk: socfpga: switch to GENMASK()

Convert the code to use GENMASK() helper instead of div_mask() macro.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Dinh Nguyen <dinguyen@opensource.altera.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>

diff --git a/drivers/clk/socfpga/clk-gate-a10.c b/drivers/clk/socfpga/clk-gate-a10.c
index 538ca504dea150d0a0f3092c098781d849799958..1cebf253e8fd44dbe22e37e1eb6a18ed63cd2f14 100644 (file)
--- a/drivers/clk/socfpga/clk-gate-a10.c
+++ b/drivers/clk/socfpga/clk-gate-a10.c
@@ -39,7 +39,7 @@ static unsigned long socfpga_gate_clk_recalc_rate(struct clk_hw *hwclk,
                div = socfpgaclk->fixed_div;
        else if (socfpgaclk->div_reg) {
                val = readl(socfpgaclk->div_reg) >> socfpgaclk->shift;
-               val &= div_mask(socfpgaclk->width);
+               val &= GENMASK(socfpgaclk->width - 1, 0);
                div = (1 << val);
        }
 

diff --git a/drivers/clk/socfpga/clk-gate.c b/drivers/clk/socfpga/clk-gate.c
index 37e0bb60ac68bec439197247579e4eb52f01a42d..aa7a6e6a15b656808d3cc9f92229125cb2baea81 100644 (file)
--- a/drivers/clk/socfpga/clk-gate.c
+++ b/drivers/clk/socfpga/clk-gate.c
@@ -105,7 +105,7 @@ static unsigned long socfpga_clk_recalc_rate(struct clk_hw *hwclk,
                div = socfpgaclk->fixed_div;
        else if (socfpgaclk->div_reg) {
                val = readl(socfpgaclk->div_reg) >> socfpgaclk->shift;
-               val &= div_mask(socfpgaclk->width);
+               val &= GENMASK(socfpgaclk->width - 1, 0);
                /* Check for GPIO_DB_CLK by its offset */
                if ((int) socfpgaclk->div_reg & SOCFPGA_GPIO_DB_CLK_OFFSET)
                        div = val + 1;

diff --git a/drivers/clk/socfpga/clk-periph-a10.c b/drivers/clk/socfpga/clk-periph-a10.c
index 64f93acbbd259729964db5fdce37c9f3e74cc266..1f397cb72e89a8ff421edfaf92cddf2fee1e16a8 100644 (file)
--- a/drivers/clk/socfpga/clk-periph-a10.c
+++ b/drivers/clk/socfpga/clk-periph-a10.c
@@ -38,7 +38,7 @@ static unsigned long clk_periclk_recalc_rate(struct clk_hw *hwclk,
                div = socfpgaclk->fixed_div;
        } else if (socfpgaclk->div_reg) {
                div = readl(socfpgaclk->div_reg) >> socfpgaclk->shift;
-               div &= div_mask(socfpgaclk->width);
+               div &= GENMASK(socfpgaclk->width - 1, 0);
                div += 1;
        } else {
                div = ((readl(socfpgaclk->hw.reg) & 0x7ff) + 1);

diff --git a/drivers/clk/socfpga/clk-periph.c b/drivers/clk/socfpga/clk-periph.c
index ab9c8164a98f87e824a79042c25e201d4a5e85c8..0c66863314933179413b87a2e004c6dbce72cc49 100644 (file)
--- a/drivers/clk/socfpga/clk-periph.c
+++ b/drivers/clk/socfpga/clk-periph.c
@@ -35,7 +35,7 @@ static unsigned long clk_periclk_recalc_rate(struct clk_hw *hwclk,
        } else {
                if (socfpgaclk->div_reg) {
                        val = readl(socfpgaclk->div_reg) >> socfpgaclk->shift;
-                       val &= div_mask(socfpgaclk->width);
+                       val &= GENMASK(socfpgaclk->width - 1, 0);
                        parent_rate /= (val + 1);
                }
                div = ((readl(socfpgaclk->hw.reg) & 0x1ff) + 1);

diff --git a/drivers/clk/socfpga/clk.h b/drivers/clk/socfpga/clk.h
index f4219202844a9d8538c8ec77c1f028be2a9aeebe..aa2741dbe81abb4704ef357ef5fcbed48842ff1a 100644 (file)
--- a/drivers/clk/socfpga/clk.h
+++ b/drivers/clk/socfpga/clk.h
@@ -26,7 +26,6 @@
 #define CLKMGR_PERPLL_SRC      0xAC
 
 #define SOCFPGA_MAX_PARENTS            5
-#define div_mask(width) ((1 << (width)) - 1)
 
 #define streq(a, b) (strcmp((a), (b)) == 0)
 #define SYSMGR_SDMMC_CTRL_SET(smplsel, drvsel) \