arm64: dts: ti: k3-am64-main: Switch ICSSG clock to core clock

ICSSG has 7 available clocks per instance. Add all the cloks to ICSSG
nodes. ICSSG currently uses ICSSG_ICLK (clk id 20) which operates at
250MHz. Switch ICSSG clock to ICSSG_CORE clock (clk id 0) which operates at
333MHz.

ICSSG_CORE clock will help get the most out of ICSSG as more cycles are
needed to fully support all ICSSG features.

This commit also changes assigned-clock-parents of coreclk-mux to
ICSSG_CORE clock from ICSSG_ICLK.

Performance update in dual mac mode
  With ICSSG_CORE Clk @ 333MHz
    Tx throughput - 934 Mbps
    Rx throughput - 914 Mbps,

  With ICSSG_ICLK clk @ 250MHz,
    Tx throughput - 920 Mbps
    Rx throughput - 706 Mbps

Signed-off-by: MD Danish Anwar <danishanwar@ti.com>
Tested-by: Wadim Egorov <w.egorov@phytec.de>
Reviewed-by: Roger Quadros <rogerq@kernel.org>
Link: https://lore.kernel.org/r/20241113110955.3876045-3-danishanwar@ti.com
Signed-off-by: Nishanth Menon <nm@ti.com>

diff --git a/arch/arm64/boot/dts/ti/k3-am64-main.dtsi b/arch/arm64/boot/dts/ti/k3-am64-main.dtsi
index c66289a4362bbcd288be6eb71de19286f433ea17..324eb44c258d37bb2da7f7152da93df51070fce4 100644 (file)
--- a/arch/arm64/boot/dts/ti/k3-am64-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-am64-main.dtsi
@@ -1227,6 +1227,15 @@
                #address-cells = <1>;
                #size-cells = <1>;
                ranges = <0x0 0x00 0x30000000 0x80000>;
+               clocks = <&k3_clks 81 0>,  /* icssg0_core_clk */
+                        <&k3_clks 81 3>,  /* icssg0_iep_clk */
+                        <&k3_clks 81 16>, /* icssg0_rgmii_mhz_250_clk */
+                        <&k3_clks 81 17>, /* icssg0_rgmii_mhz_50_clk */
+                        <&k3_clks 81 18>, /* icssg0_rgmii_mhz_5_clk */
+                        <&k3_clks 81 19>, /* icssg0_uart_clk */
+                        <&k3_clks 81 20>; /* icssg0_iclk */
+               assigned-clocks = <&k3_clks 81 0>;
+               assigned-clock-parents = <&k3_clks 81 2>;
 
                icssg0_mem: memories@0 {
                        reg = <0x0 0x2000>,
@@ -1252,7 +1261,7 @@
                                        clocks = <&k3_clks 81 0>,  /* icssg0_core_clk */
                                                 <&k3_clks 81 20>; /* icssg0_iclk */
                                        assigned-clocks = <&icssg0_coreclk_mux>;
-                                       assigned-clock-parents = <&k3_clks 81 20>;
+                                       assigned-clock-parents = <&k3_clks 81 0>;
                                };
 
                                icssg0_iepclk_mux: iepclk-mux@30 {
@@ -1397,6 +1406,15 @@
                #address-cells = <1>;
                #size-cells = <1>;
                ranges = <0x0 0x00 0x30080000 0x80000>;
+               clocks = <&k3_clks 82 0>,  /* icssg1_core_clk */
+                        <&k3_clks 82 3>,  /* icssg1_iep_clk */
+                        <&k3_clks 82 16>, /* icssg1_rgmii_mhz_250_clk */
+                        <&k3_clks 82 17>, /* icssg1_rgmii_mhz_50_clk */
+                        <&k3_clks 82 18>, /* icssg1_rgmii_mhz_5_clk */
+                        <&k3_clks 82 19>, /* icssg1_uart_clk */
+                        <&k3_clks 82 20>; /* icssg1_iclk */
+               assigned-clocks = <&k3_clks 82 0>;
+               assigned-clock-parents = <&k3_clks 82 2>;
 
                icssg1_mem: memories@0 {
                        reg = <0x0 0x2000>,
@@ -1422,7 +1440,7 @@
                                        clocks = <&k3_clks 82 0>,   /* icssg1_core_clk */
                                                 <&k3_clks 82 20>;  /* icssg1_iclk */
                                        assigned-clocks = <&icssg1_coreclk_mux>;
-                                       assigned-clock-parents = <&k3_clks 82 20>;
+                                       assigned-clock-parents = <&k3_clks 82 0>;
                                };
 
                                icssg1_iepclk_mux: iepclk-mux@30 {