drm/i915/gt: Nuke gen2_irq_{enable,disable}()

We've determined that accessing the (supposedly) 16bit
interrupt registers on gen2 as 32bit works just fine.
We already dropped the special case from the main interrupt
code, do so also for the gt interrupt stuff.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20241008214349.23331-2-ville.syrjala@linux.intel.com
Reviewed-by: Jani Nikula <jani.nikula@intel.com>

diff --git a/drivers/gpu/drm/i915/gt/gen2_engine_cs.c b/drivers/gpu/drm/i915/gt/gen2_engine_cs.c
index 8fe0499308ffe533232efcf944f5c3c39016e921..54077cab8e16658e04df3d9b3d14ee055dfd5e9d 100644 (file)
--- a/drivers/gpu/drm/i915/gt/gen2_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/gen2_engine_cs.c
@@ -290,23 +290,6 @@ int gen4_emit_bb_start(struct i915_request *rq,
        return 0;
 }
 
-void gen2_irq_enable(struct intel_engine_cs *engine)
-{
-       struct drm_i915_private *i915 = engine->i915;
-
-       i915->irq_mask &= ~engine->irq_enable_mask;
-       intel_uncore_write16(&i915->uncore, GEN2_IMR, i915->irq_mask);
-       ENGINE_POSTING_READ16(engine, RING_IMR);
-}
-
-void gen2_irq_disable(struct intel_engine_cs *engine)
-{
-       struct drm_i915_private *i915 = engine->i915;
-
-       i915->irq_mask |= engine->irq_enable_mask;
-       intel_uncore_write16(&i915->uncore, GEN2_IMR, i915->irq_mask);
-}
-
 void gen3_irq_enable(struct intel_engine_cs *engine)
 {
        engine->i915->irq_mask &= ~engine->irq_enable_mask;

diff --git a/drivers/gpu/drm/i915/gt/gen2_engine_cs.h b/drivers/gpu/drm/i915/gt/gen2_engine_cs.h
index a5cd64a65c9e5958f264235e37e4162ac4e5af76..2f707620b3d44073bc85d712fe808f9882b53f4d 100644 (file)
--- a/drivers/gpu/drm/i915/gt/gen2_engine_cs.h
+++ b/drivers/gpu/drm/i915/gt/gen2_engine_cs.h
@@ -28,8 +28,6 @@ int gen4_emit_bb_start(struct i915_request *rq,
                       u64 offset, u32 length,
                       unsigned int dispatch_flags);
 
-void gen2_irq_enable(struct intel_engine_cs *engine);
-void gen2_irq_disable(struct intel_engine_cs *engine);
 void gen3_irq_enable(struct intel_engine_cs *engine);
 void gen3_irq_disable(struct intel_engine_cs *engine);
 void gen5_irq_enable(struct intel_engine_cs *engine);

diff --git a/drivers/gpu/drm/i915/gt/intel_ring_submission.c b/drivers/gpu/drm/i915/gt/intel_ring_submission.c
index 72277bc8322e81b63cf01f892d94f8f0881fff0f..694cb79d5452b5fed798f7ddb3b6b4ab80f1e48e 100644 (file)
--- a/drivers/gpu/drm/i915/gt/intel_ring_submission.c
+++ b/drivers/gpu/drm/i915/gt/intel_ring_submission.c
@@ -1090,12 +1090,9 @@ static void setup_irq(struct intel_engine_cs *engine)
        } else if (GRAPHICS_VER(i915) >= 5) {
                engine->irq_enable = gen5_irq_enable;
                engine->irq_disable = gen5_irq_disable;
-       } else if (GRAPHICS_VER(i915) >= 3) {
+       } else {
                engine->irq_enable = gen3_irq_enable;
                engine->irq_disable = gen3_irq_disable;
-       } else {
-               engine->irq_enable = gen2_irq_enable;
-               engine->irq_disable = gen2_irq_disable;
        }
 }