net: phy: ti: add PHY_RST_AFTER_CLK_EN flag

DP83848	datasheet (section 4.7.2) indicates that the reset pin should be
toggled after the clocks are running. Add the PHY_RST_AFTER_CLK_EN to
make sure that this indication is respected.

In my experience not having this flag enabled would lead to, on some
boots, the wrong MII mode being selected if the PHY was initialized on
the bootloader and was receiving data during Linux boot.

Signed-off-by: Diogo Silva <diogompaissilva@gmail.com>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Fixes: 34e45ad9378c ("net: phy: dp83848: Add TI DP83848 Ethernet PHY")
Link: https://patch.msgid.link/20241102151504.811306-1-paissilva@ld-100007.ds1.internal
Signed-off-by: Jakub Kicinski <kuba@kernel.org>

diff --git a/drivers/net/phy/dp83848.c b/drivers/net/phy/dp83848.c
index 937061acfc613a203ee8df72158df4d41ed1c96a..351411f0aa6f471d47112fcbdadf5aa4139fa895 100644 (file)
--- a/drivers/net/phy/dp83848.c
+++ b/drivers/net/phy/dp83848.c
@@ -147,6 +147,8 @@ MODULE_DEVICE_TABLE(mdio, dp83848_tbl);
                /* IRQ related */                               \
                .config_intr    = dp83848_config_intr,          \
                .handle_interrupt = dp83848_handle_interrupt,   \
+                                                               \
+               .flags          = PHY_RST_AFTER_CLK_EN,         \
        }
 
 static struct phy_driver dp83848_driver[] = {