]> www.infradead.org Git - users/borneoa/openocd-next.git/commitdiff
flash/stm32l4x: add STM32C071xx support
authorDavid (Pololu) <dev-david@pololu.com>
Wed, 18 Dec 2024 21:49:00 +0000 (13:49 -0800)
committerTomas Vanek <vanekt@fbl.cz>
Mon, 6 Jan 2025 05:01:21 +0000 (05:01 +0000)
I successfully programmed a NUCLEO-C071RB with these changes.

Change-Id: Ib57a77fa18f8a0e8c882e2250d6111c588d76887
Signed-off-by: David (Pololu) <dev-david@pololu.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/8525
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
doc/openocd.texi
src/flash/nor/stm32l4x.c
src/flash/nor/stm32l4x.h
tcl/board/st_nucleo_c0.cfg [new file with mode: 0644]

index 594f7a7f0cd50a3c0ab9030c4cf2ccd277d9863c..7c5f84c55971e79165acb5a336870e54a0b517a2 100644 (file)
@@ -8001,7 +8001,7 @@ The @var{num} parameter is a value shown by @command{flash banks}.
 @end deffn
 
 @deffn {Flash Driver} {stm32l4x}
-All members of the STM32 G0, G4, L4, L4+, L5, U0, U5, WB and WL
+All members of the STM32 C0, G0, G4, L4, L4+, L5, U0, U5, WB and WL
 microcontroller families from STMicroelectronics include internal flash
 and use ARM Cortex-M0+, M4 and M33 cores.
 The driver automatically recognizes a number of these chips using
index d2e8f305039b7b9a83a311051cecdd31a4c2ef7f..3062fca72a0720effad0a1a5f5635b56350d25b8 100644 (file)
@@ -303,6 +303,10 @@ static const struct stm32l4_rev stm32c03xx_revs[] = {
        { 0x1000, "A" }, { 0x1001, "Z" },
 };
 
+static const struct stm32l4_rev stm32c071xx_revs[] = {
+       { 0x1001, "Z" },
+};
+
 static const struct stm32l4_rev stm32g05_g06xx_revs[] = {
        { 0x1000, "A" },
 };
@@ -442,6 +446,18 @@ static const struct stm32l4_part_info stm32l4_parts[] = {
          .otp_base              = 0x1FFF7000,
          .otp_size              = 1024,
        },
+       {
+         .id                    = DEVID_STM32C071XX,
+         .revs                  = stm32c071xx_revs,
+         .num_revs              = ARRAY_SIZE(stm32c071xx_revs),
+         .device_str            = "STM32C071xx",
+         .max_flash_size_kb     = 128,
+         .flags                 = F_NONE,
+         .flash_regs_base       = 0x40022000,
+         .fsize_addr            = 0x1FFF75A0,
+         .otp_base              = 0x1FFF7000,
+         .otp_size              = 1024,
+       },
        {
          .id                    = DEVID_STM32U53_U54XX,
          .revs                  = stm32u53_u54xx_revs,
@@ -1989,6 +2005,7 @@ static int stm32l4_probe(struct flash_bank *bank)
        case DEVID_STM32L43_L44XX:
        case DEVID_STM32C01XX:
        case DEVID_STM32C03XX:
+       case DEVID_STM32C071XX:
        case DEVID_STM32G05_G06XX:
        case DEVID_STM32G07_G08XX:
        case DEVID_STM32U031XX:
index b1e8f9870d7b79ae0185f23bd7ff4d404c62e44f..f152c9f30ae43bd746df0214a8f12268c010ef60 100644 (file)
 #define DEVID_STM32U57_U58XX   0x482
 #define DEVID_STM32U073_U083XX 0x489
 #define DEVID_STM32WBA5X               0x492
+#define DEVID_STM32C071XX              0x493
 #define DEVID_STM32WB1XX               0x494
 #define DEVID_STM32WB5XX               0x495
 #define DEVID_STM32WB3XX               0x496
diff --git a/tcl/board/st_nucleo_c0.cfg b/tcl/board/st_nucleo_c0.cfg
new file mode 100644 (file)
index 0000000..7d07675
--- /dev/null
@@ -0,0 +1,9 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+source [find interface/stlink.cfg]
+
+transport select dapdirect_swd
+
+source [find target/stm32c0x.cfg]
+
+reset_config srst_only