lss_l1_2 = rtsx_check_dev_flag(pcr, ASPM_L1_2_EN)
                        | rtsx_check_dev_flag(pcr, PM_L1_2_EN);
 
+       rtsx_pci_write_register(pcr, ASPM_FORCE_CTL, 0xFF, 0);
        if (lss_l1_2) {
                pcr_dbg(pcr, "Set parameters for L1.2.");
                rtsx_pci_write_register(pcr, PWR_GLOBAL_CTRL,
         * to drive low, and we forcibly request clock.
         */
        if (option->force_clkreq_0)
-               rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PETXCFG,
+               rtsx_pci_write_register(pcr, PETXCFG,
                                 FORCE_CLKREQ_DELINK_MASK, FORCE_CLKREQ_LOW);
        else
-               rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PETXCFG,
+               rtsx_pci_write_register(pcr, PETXCFG,
                                 FORCE_CLKREQ_DELINK_MASK, FORCE_CLKREQ_HIGH);
 
        return 0;
        option->ocp_en = 1;
        if (option->ocp_en)
                hw_param->interrupt_en |= SD_OC_INT_EN;
-       hw_param->ocp_glitch =  SDVIO_OCP_GLITCH_800U | SDVIO_OCP_GLITCH_800U;
+       hw_param->ocp_glitch =  SD_OCP_GLITCH_100U | SDVIO_OCP_GLITCH_800U;
        option->sd_400mA_ocp_thd = RTS5260_DVCC_OCP_THD_550;
        option->sd_800mA_ocp_thd = RTS5260_DVCC_OCP_THD_970;
 }