return false;
 }
 
+bool bnxt_bs_trace_avail(struct bnxt *bp, u16 type)
+{
+       u32 flags = bp->ctx->ctx_arr[type].flags;
+
+       return (flags & BNXT_CTX_MEM_TYPE_VALID) &&
+               ((flags & BNXT_CTX_MEM_FW_TRACE) ||
+                (flags & BNXT_CTX_MEM_FW_BIN_TRACE));
+}
+
 #define BNXT_EVENT_THERMAL_CURRENT_TEMP(data2)                         \
        ((data2) &                                                      \
          ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA2_CURRENT_TEMP_MASK)
 {
        struct bnxt_ctx_mem_info *ctx = bp->ctx;
        struct bnxt_ctx_mem_type *ctxm;
-       u16 last_type;
+       u16 last_type = BNXT_CTX_INV;
        int rc = 0;
        u16 type;
 
-       if (!ena)
-               return 0;
-       else if (ena & FUNC_BACKING_STORE_CFG_REQ_ENABLES_TIM)
-               last_type = BNXT_CTX_MAX - 1;
-       else
-               last_type = BNXT_CTX_L2_MAX - 1;
+       for (type = BNXT_CTX_SRT; type <= BNXT_CTX_RIGP1; type++) {
+               ctxm = &ctx->ctx_arr[type];
+               if (!bnxt_bs_trace_avail(bp, type))
+                       continue;
+               if (!ctxm->mem_valid) {
+                       rc = bnxt_setup_ctxm_pg_tbls(bp, ctxm,
+                                                    ctxm->max_entries, 1);
+                       if (rc) {
+                               netdev_warn(bp->dev, "Unable to setup ctx page for type:0x%x.\n",
+                                           type);
+                               continue;
+                       }
+                       last_type = type;
+               }
+       }
+
+       if (last_type == BNXT_CTX_INV) {
+               if (!ena)
+                       return 0;
+               else if (ena & FUNC_BACKING_STORE_CFG_REQ_ENABLES_TIM)
+                       last_type = BNXT_CTX_MAX - 1;
+               else
+                       last_type = BNXT_CTX_L2_MAX - 1;
+       }
        ctx->ctx_arr[last_type].last = 1;
 
        for (type = 0 ; type < BNXT_CTX_V2_MAX; type++) {
 
        ctxm->last = 0;
 
-       if (ctxm->mem_valid && !force)
+       if (ctxm->mem_valid && !force && (ctxm->flags & BNXT_CTX_MEM_PERSIST))
                return;
 
        ctx_pg = ctxm->pg_info;
 
        u16     entry_size;
        u32     flags;
 #define BNXT_CTX_MEM_TYPE_VALID FUNC_BACKING_STORE_QCAPS_V2_RESP_FLAGS_TYPE_VALID
+#define BNXT_CTX_MEM_FW_TRACE          \
+       FUNC_BACKING_STORE_QCAPS_V2_RESP_FLAGS_FW_DBG_TRACE
+#define BNXT_CTX_MEM_FW_BIN_TRACE      \
+       FUNC_BACKING_STORE_QCAPS_V2_RESP_FLAGS_FW_BIN_DBG_TRACE
+#define BNXT_CTX_MEM_PERSIST           \
+       FUNC_BACKING_STORE_QCAPS_V2_RESP_FLAGS_NEXT_BS_OFFSET
+
        u32     instance_bmap;
        u8      init_value;
        u8      entry_multiple;
 #define BNXT_CTX_FTQM  FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_FP_TQM_RING
 #define BNXT_CTX_MRAV  FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_MRAV
 #define BNXT_CTX_TIM   FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_TIM
-#define BNXT_CTX_TKC   FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_TKC
-#define BNXT_CTX_RKC   FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_RKC
+#define BNXT_CTX_TCK   FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_TX_CK
+#define BNXT_CTX_RCK   FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_RX_CK
 #define BNXT_CTX_MTQM  FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_MP_TQM_RING
 #define BNXT_CTX_SQDBS FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_SQ_DB_SHADOW
 #define BNXT_CTX_RQDBS FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_RQ_DB_SHADOW
 #define BNXT_CTX_SRQDBS        FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_SRQ_DB_SHADOW
 #define BNXT_CTX_CQDBS FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_CQ_DB_SHADOW
-#define BNXT_CTX_QTKC  FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_QUIC_TKC
-#define BNXT_CTX_QRKC  FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_QUIC_RKC
 #define BNXT_CTX_TBLSC FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_TBL_SCOPE
 #define BNXT_CTX_XPAR  FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_XID_PARTITION
+#define BNXT_CTX_SRT   FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_SRT_TRACE
+#define BNXT_CTX_SRT2  FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_SRT2_TRACE
+#define BNXT_CTX_CRT   FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_CRT_TRACE
+#define BNXT_CTX_CRT2  FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_CRT2_TRACE
+#define BNXT_CTX_RIGP0 FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_RIGP0_TRACE
+#define BNXT_CTX_L2HWRM        FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_L2_HWRM_TRACE
+#define BNXT_CTX_REHWRM        FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_ROCE_HWRM_TRACE
+#define BNXT_CTX_CA0   FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_CA0_TRACE
+#define BNXT_CTX_CA1   FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_CA1_TRACE
+#define BNXT_CTX_CA2   FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_CA2_TRACE
+#define BNXT_CTX_RIGP1 FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_RIGP1_TRACE
 
 #define BNXT_CTX_MAX   (BNXT_CTX_TIM + 1)
 #define BNXT_CTX_L2_MAX        (BNXT_CTX_FTQM + 1)
-#define BNXT_CTX_V2_MAX        (BNXT_CTX_XPAR + 1)
+#define BNXT_CTX_V2_MAX        (BNXT_CTX_RIGP1 + 1)
 #define BNXT_CTX_INV   ((u16)-1)
 
 struct bnxt_ctx_mem_info {
                       u16 prod, gfp_t gfp);
 void bnxt_reuse_rx_data(struct bnxt_rx_ring_info *rxr, u16 cons, void *data);
 u32 bnxt_fw_health_readl(struct bnxt *bp, int reg_idx);
+bool bnxt_bs_trace_avail(struct bnxt *bp, u16 type);
 void bnxt_set_tpa_flags(struct bnxt *bp);
 void bnxt_set_ring_params(struct bnxt *);
 int bnxt_set_rx_skb_mode(struct bnxt *bp, bool page_mode);