clk: ast2600: Fix AHB clock divider for A1

[ Upstream commit 2d491066ccd4286538450c227fc5094ceb04b494 ]

The latest specs for the AST2600 A1 chip include some different bit
definitions for calculating the AHB clock divider. Implement these in
order to get the correct AHB clock value in Linux.

Signed-off-by: Eddie James <eajames@linux.ibm.com>
Link: https://lkml.kernel.org/r/20200408203616.4031-1-eajames@linux.ibm.com
Fixes: d3d04f6c330a ("clk: Add support for AST2600 SoC")
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>

diff --git a/drivers/clk/clk-ast2600.c b/drivers/clk/clk-ast2600.c
index b1318e6b655bcc615cef2354d96278ea71f836ea..675cab6fa7814054cc610d9355aa9809a2a5e1ca 100644 (file)
--- a/drivers/clk/clk-ast2600.c
+++ b/drivers/clk/clk-ast2600.c
@@ -599,14 +599,22 @@ static const u32 ast2600_a0_axi_ahb_div_table[] = {
        2, 2, 3, 5,
 };
 
-static const u32 ast2600_a1_axi_ahb_div_table[] = {
-       4, 6, 2, 4,
+static const u32 ast2600_a1_axi_ahb_div0_tbl[] = {
+       3, 2, 3, 4,
+};
+
+static const u32 ast2600_a1_axi_ahb_div1_tbl[] = {
+       3, 4, 6, 8,
+};
+
+static const u32 ast2600_a1_axi_ahb200_tbl[] = {
+       3, 4, 3, 4, 2, 2, 2, 2,
 };
 
 static void __init aspeed_g6_cc(struct regmap *map)
 {
        struct clk_hw *hw;
-       u32 val, div, chip_id, axi_div, ahb_div;
+       u32 val, div, divbits, chip_id, axi_div, ahb_div;
 
        clk_hw_register_fixed_rate(NULL, "clkin", NULL, 0, 25000000);
 
@@ -636,11 +644,22 @@ static void __init aspeed_g6_cc(struct regmap *map)
        else
                axi_div = 2;
 
+       divbits = (val >> 11) & 0x3;
        regmap_read(map, ASPEED_G6_SILICON_REV, &chip_id);
-       if (chip_id & BIT(16))
-               ahb_div = ast2600_a1_axi_ahb_div_table[(val >> 11) & 0x3];
-       else
+       if (chip_id & BIT(16)) {
+               if (!divbits) {
+                       ahb_div = ast2600_a1_axi_ahb200_tbl[(val >> 8) & 0x3];
+                       if (val & BIT(16))
+                               ahb_div *= 2;
+               } else {
+                       if (val & BIT(16))
+                               ahb_div = ast2600_a1_axi_ahb_div1_tbl[divbits];
+                       else
+                               ahb_div = ast2600_a1_axi_ahb_div0_tbl[divbits];
+               }
+       } else {
                ahb_div = ast2600_a0_axi_ahb_div_table[(val >> 11) & 0x3];
+       }
 
        hw = clk_hw_register_fixed_factor(NULL, "ahb", "hpll", 0, 1, axi_div * ahb_div);
        aspeed_g6_clk_data->hws[ASPEED_CLK_AHB] = hw;