},
 };
 
+static const struct regulator_bulk_data sa8775p_dsi_regulators[] = {
+       { .supply = "vdda", .init_load_uA = 8300 },    /* 1.2 V */
+       { .supply = "refgen" },
+};
+
+static const struct msm_dsi_config sa8775p_dsi_cfg = {
+       .io_offset = DSI_6G_REG_SHIFT,
+       .regulator_data = sa8775p_dsi_regulators,
+       .num_regulators = ARRAY_SIZE(sa8775p_dsi_regulators),
+       .bus_clk_names = dsi_v2_4_clk_names,
+       .num_bus_clks = ARRAY_SIZE(dsi_v2_4_clk_names),
+       .io_start = {
+               { 0xae94000, 0xae96000 },
+       },
+};
+
 static const struct msm_dsi_host_cfg_ops msm_dsi_v2_host_ops = {
        .link_clk_set_rate = dsi_link_clk_set_rate_v2,
        .link_clk_enable = dsi_link_clk_enable_v2,
                &sdm845_dsi_cfg, &msm_dsi_6g_v2_host_ops},
        {MSM_DSI_VER_MAJOR_6G, MSM_DSI_6G_VER_MINOR_V2_5_0,
                &sc7280_dsi_cfg, &msm_dsi_6g_v2_host_ops},
+       {MSM_DSI_VER_MAJOR_6G, MSM_DSI_6G_VER_MINOR_V2_5_1,
+               &sa8775p_dsi_cfg, &msm_dsi_6g_v2_host_ops},
        {MSM_DSI_VER_MAJOR_6G, MSM_DSI_6G_VER_MINOR_V2_6_0,
                &sdm845_dsi_cfg, &msm_dsi_6g_v2_host_ops},
        {MSM_DSI_VER_MAJOR_6G, MSM_DSI_6G_VER_MINOR_V2_7_0,
 
 #define MSM_DSI_6G_VER_MINOR_V2_4_0    0x20040000
 #define MSM_DSI_6G_VER_MINOR_V2_4_1    0x20040001
 #define MSM_DSI_6G_VER_MINOR_V2_5_0    0x20050000
+#define MSM_DSI_6G_VER_MINOR_V2_5_1    0x20050001
 #define MSM_DSI_6G_VER_MINOR_V2_6_0    0x20060000
 #define MSM_DSI_6G_VER_MINOR_V2_7_0    0x20070000
 #define MSM_DSI_6G_VER_MINOR_V2_8_0    0x20080000