u32 dspaddr_offset = plane_state->view.color_plane[0].offset;
enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;
- intel_de_write_fw(dev_priv, DSPADDR_VLV(i9xx_plane),
+ intel_de_write_fw(dev_priv, DSPADDR_VLV(dev_priv, i9xx_plane),
intel_plane_ggtt_offset(plane_state) + dspaddr_offset);
}
#include "intel_display_reg_defs.h"
#define _DSPAADDR_VLV 0x7017C /* vlv/chv */
-#define DSPADDR_VLV(plane) _MMIO_PIPE2(dev_priv, plane, _DSPAADDR_VLV)
+#define DSPADDR_VLV(dev_priv, plane) _MMIO_PIPE2(dev_priv, plane, _DSPAADDR_VLV)
#define _DSPACNTR 0x70180
#define DSPCNTR(plane) _MMIO_PIPE2(dev_priv, plane, _DSPACNTR)