drm/i915: replace random CNL comments

Cleanup remaining cases that we find CNL in the codebase.

Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210728215946.1573015-22-lucas.demarchi@intel.com

diff --git a/drivers/gpu/drm/i915/display/intel_bios.c b/drivers/gpu/drm/i915/display/intel_bios.c
index 4172c8ee6aa6ea3e8d42f84db9516a0c33f32e18..e86e6ed2d3bf20613e45f2e86882fd511d850863 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_bios.c
+++ b/drivers/gpu/drm/i915/display/intel_bios.c
@@ -1998,7 +1998,7 @@ static void parse_ddi_port(struct drm_i915_private *i915,
                            "Port %c VBT HDMI boost level: %d\n",
                            port_name(port), hdmi_boost_level);
 
-       /* DP max link rate for CNL+ */
+       /* DP max link rate for GLK+ */
        if (i915->vbt.version >= 216) {
                if (i915->vbt.version >= 230)
                        info->dp_max_link_rate = parse_bdb_230_dp_max_link_rate(child->dp_max_link_rate);

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index aed4d4bf530aa6a666287df4ee3077ef795d851b..0efea2a17e1020c545bda200fa11ab870de1feb6 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -3575,7 +3575,7 @@ static void hsw_crtc_enable(struct intel_atomic_state *state,
 
        crtc->active = true;
 
-       /* Display WA #1180: WaDisableScalarClockGating: glk, cnl */
+       /* Display WA #1180: WaDisableScalarClockGating: glk */
        psl_clkgate_wa = DISPLAY_VER(dev_priv) == 10 &&
                new_crtc_state->pch_pfit.enabled;
        if (psl_clkgate_wa)
@@ -9870,7 +9870,7 @@ static int intel_atomic_check_async(struct intel_atomic_state *state)
 
                /*
                 * FIXME: This check is kept generic for all platforms.
-                * Need to verify this for all gen9 and gen10 platforms to enable
+                * Need to verify this for all gen9 platforms to enable
                 * this selectively if required.
                 */
                switch (new_plane_state->hw.fb->modifier) {
@@ -13257,7 +13257,7 @@ get_encoder_power_domains(struct drm_i915_private *dev_priv)
 static void intel_early_display_was(struct drm_i915_private *dev_priv)
 {
        /*
-        * Display WA #1185 WaDisableDARBFClkGating:cnl,glk,icl,ehl,tgl
+        * Display WA #1185 WaDisableDARBFClkGating:glk,icl,ehl,tgl
         * Also known as Wa_14010480278.
         */
        if (IS_DISPLAY_VER(dev_priv, 10, 12))

diff --git a/drivers/gpu/drm/i915/display/intel_dp_aux.c b/drivers/gpu/drm/i915/display/intel_dp_aux.c
index 7c048d2ecf437a6e37a57be3616ed0f45b605420..f483f479dd0b2207c8bcf5f56a253d4e9f1a217e 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_dp_aux.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_aux.c
@@ -158,7 +158,6 @@ static u32 skl_get_aux_send_ctl(struct intel_dp *intel_dp,
        /*
         * Max timeout values:
         * SKL-GLK: 1.6ms
-        * CNL: 3.2ms
         * ICL+: 4ms
         */
        ret = DP_AUX_CH_CTL_SEND_BUSY |

diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
index 7fd031a70cfd35d6734ef4a52abbc17ab7942b01..30e0aa5ca1093e568f892fc3e5e1647d120ad852 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
@@ -204,9 +204,8 @@ struct intel_dpll_hw_state {
        /* HDMI only, 0 when used for DP */
        u32 cfgcr1, cfgcr2;
 
-       /* cnl */
+       /* icl */
        u32 cfgcr0;
-       /* CNL also uses cfgcr1 */
 
        /* bxt */
        u32 ebb0, ebb4, pll0, pll1, pll2, pll3, pll6, pll8, pll9, pll10, pcsdw12;

diff --git a/drivers/gpu/drm/i915/display/intel_gmbus.c b/drivers/gpu/drm/i915/display/intel_gmbus.c
index fcf47f98ea365ef6add01c50f04dcfac101cc9eb..ceb1bf8a8c3c2600be5bcb35e42be312e4ec9cc0 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_gmbus.c
+++ b/drivers/gpu/drm/i915/display/intel_gmbus.c
@@ -600,7 +600,7 @@ do_gmbus_xfer(struct i2c_adapter *adapter, struct i2c_msg *msgs, int num,
        int i = 0, inc, try = 0;
        int ret = 0;
 
-       /* Display WA #0868: skl,bxt,kbl,cfl,glk,cnl */
+       /* Display WA #0868: skl,bxt,kbl,cfl,glk */
        if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
                bxt_gmbus_clock_gating(dev_priv, false);
        else if (HAS_PCH_SPT(dev_priv) || HAS_PCH_CNP(dev_priv))
@@ -713,7 +713,7 @@ timeout:
        ret = -EAGAIN;
 
 out:
-       /* Display WA #0868: skl,bxt,kbl,cfl,glk,cnl */
+       /* Display WA #0868: skl,bxt,kbl,cfl,glk */
        if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
                bxt_gmbus_clock_gating(dev_priv, true);
        else if (HAS_PCH_SPT(dev_priv) || HAS_PCH_CNP(dev_priv))

diff --git a/drivers/gpu/drm/i915/display/intel_vbt_defs.h b/drivers/gpu/drm/i915/display/intel_vbt_defs.h
index dbe24d7e73759c42d24360f3d09733b6221528c6..330077c2e5883df6810c5ceca805e2f9dad443da 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_vbt_defs.h
+++ b/drivers/gpu/drm/i915/display/intel_vbt_defs.h
@@ -456,7 +456,7 @@ struct child_device_config {
        u16 dp_gpio_pin_num;                                    /* 195 */
        u8 dp_iboost_level:4;                                   /* 196 */
        u8 hdmi_iboost_level:4;                                 /* 196 */
-       u8 dp_max_link_rate:3;                                  /* 216/230 CNL+ */
+       u8 dp_max_link_rate:3;                                  /* 216/230 GLK+ */
        u8 dp_max_link_rate_reserved:5;                         /* 216/230 */
 } __packed;
 

diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c
index 0f40f8b07724f137316d8cc58f8b5d7316ab59e5..724e7b04f3b63c0fa09c424a4d9f169aec15cfe4 100644 (file)
--- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
+++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
@@ -1270,7 +1270,7 @@ static int skl_plane_check_dst_coordinates(const struct intel_crtc_state *crtc_s
        int pipe_src_w = crtc_state->pipe_src_w;
 
        /*
-        * Display WA #1175: cnl,glk
+        * Display WA #1175: glk
         * Planes other than the cursor may cause FIFO underflow and display
         * corruption if starting less than 4 pixels from the right edge of
         * the screen.

diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
index 616ccec41d763a6e6ff5bcc67a8ce893d99d1cb7..316edad22eb0b594378f36f6a42d9db6e8622895 100644 (file)
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -105,7 +105,7 @@ enum intel_platform {
 #define INTEL_SUBPLATFORM_ULT  (0)
 #define INTEL_SUBPLATFORM_ULX  (1)
 
-/* CNL/ICL */
+/* ICL */
 #define INTEL_SUBPLATFORM_PORTF        (0)
 
 /* DG2 */