qspi_writel(q, reg, q->iobase + QUADSPI_MCR);
 }
 
-static void fsl_qspi_select_mem(struct fsl_qspi *q, struct spi_device *spi)
+static void fsl_qspi_select_mem(struct fsl_qspi *q, struct spi_device *spi,
+                               const struct spi_mem_op *op)
 {
-       unsigned long rate = spi->max_speed_hz;
+       unsigned long rate = op->max_freq;
        int ret;
 
        if (q->selected == spi_get_chipselect(spi, 0))
        fsl_qspi_readl_poll_tout(q, base + QUADSPI_SR, (QUADSPI_SR_IP_ACC_MASK |
                                 QUADSPI_SR_AHB_ACC_MASK), 10, 1000);
 
-       fsl_qspi_select_mem(q, mem->spi);
+       fsl_qspi_select_mem(q, mem->spi, op);
 
        if (needs_amba_base_offset(q))
                addr_offset = q->memmap_phy;
        .get_name = fsl_qspi_get_name,
 };
 
+static const struct spi_controller_mem_caps fsl_qspi_mem_caps = {
+       .per_op_freq = true,
+};
+
 static int fsl_qspi_probe(struct platform_device *pdev)
 {
        struct spi_controller *ctlr;
        ctlr->bus_num = -1;
        ctlr->num_chipselect = 4;
        ctlr->mem_ops = &fsl_qspi_mem_ops;
+       ctlr->mem_caps = &fsl_qspi_mem_caps;
 
        fsl_qspi_default_setup(q);