arm64: dts: mediatek: mt7988: Add xsphy for ssusb0/pcie2

First usb and third pcie controller on mt7988 need a xs-phy to work
properly.

Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://lore.kernel.org/r/20250422132438.15735-8-linux@fw-web.de
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>

diff --git a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi
index 88b56a24efcab0194da9f7de197f8e2274d71c44..a59f8708f0efc262508e8d425134b4ffe2dcda64 100644 (file)
--- a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi
@@ -334,6 +334,8 @@
                                 <&infracfg CLK_INFRA_133M_USB_HCK>,
                                 <&infracfg CLK_INFRA_USB_XHCI>;
                        clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck", "xhci_ck";
+                       phys = <&xphyu2port0 PHY_TYPE_USB2>,
+                              <&xphyu3port0 PHY_TYPE_USB3>;
                        status = "disabled";
                };
 
@@ -398,6 +400,9 @@
                        pinctrl-0 = <&pcie2_pins>;
                        status = "disabled";
 
+                       phys = <&xphyu3port0 PHY_TYPE_PCIE>;
+                       phy-names = "pcie-phy";
+
                        #interrupt-cells = <1>;
                        interrupt-map-mask = <0 0 0 0x7>;
                        interrupt-map = <0 0 0 1 &pcie_intc2 0>,
@@ -548,6 +553,37 @@
                        };
                };
 
+
+               topmisc: system-controller@11d10084 {
+                       compatible = "mediatek,mt7988-topmisc",
+                                    "syscon";
+                       reg = <0 0x11d10084 0 0xff80>;
+               };
+
+               xs-phy@11e10000 {
+                       compatible = "mediatek,mt7988-xsphy",
+                                    "mediatek,xsphy";
+                       #address-cells = <2>;
+                       #size-cells = <2>;
+                       ranges;
+                       status = "disabled";
+
+                       xphyu2port0: usb-phy@11e10000 {
+                               reg = <0 0x11e10000 0 0x400>;
+                               clocks = <&infracfg CLK_INFRA_USB_UTMI>;
+                               clock-names = "ref";
+                               #phy-cells = <1>;
+                       };
+
+                       xphyu3port0: usb-phy@11e13000 {
+                               reg = <0 0x11e13400 0 0x500>;
+                               clocks = <&infracfg CLK_INFRA_USB_PIPE>;
+                               clock-names = "ref";
+                               #phy-cells = <1>;
+                               mediatek,syscon-type = <&topmisc 0x194 0>;
+                       };
+               };
+
                clock-controller@11f40000 {
                        compatible = "mediatek,mt7988-xfi-pll";
                        reg = <0 0x11f40000 0 0x1000>;