arm64: dts: freescale: imx8-ss-lsio: add support for lsio_pwm0-3

Add support for lsio_pwm0-3.

Signed-off-by: Philippe Schenker <philippe.schenker@toradex.com>
Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com>
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-lsio.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-lsio.dtsi
index 1f3d225e64ece966390d4bdc967f538034a4d977..62b7f7a3e1bc9a2944059f8d519527d4ce0bb623 100644 (file)
--- a/arch/arm64/boot/dts/freescale/imx8-ss-lsio.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8-ss-lsio.dtsi
@@ -28,6 +28,54 @@ lsio_subsys: bus@5d000000 {
                clock-output-names = "lsio_bus_clk";
        };
 
+       lsio_pwm0: pwm@5d000000 {
+               compatible = "fsl,imx27-pwm";
+               reg = <0x5d000000 0x10000>;
+               clock-names = "ipg", "per";
+               clocks = <&pwm0_lpcg 4>,
+                        <&pwm0_lpcg 1>;
+               assigned-clocks = <&clk IMX_SC_R_PWM_0 IMX_SC_PM_CLK_PER>;
+               assigned-clock-rates = <24000000>;
+               #pwm-cells = <2>;
+               status = "disabled";
+       };
+
+       lsio_pwm1: pwm@5d010000 {
+               compatible = "fsl,imx27-pwm";
+               reg = <0x5d010000 0x10000>;
+               clock-names = "ipg", "per";
+               clocks = <&pwm1_lpcg 4>,
+                        <&pwm1_lpcg 1>;
+               assigned-clocks = <&clk IMX_SC_R_PWM_1 IMX_SC_PM_CLK_PER>;
+               assigned-clock-rates = <24000000>;
+               #pwm-cells = <2>;
+               status = "disabled";
+       };
+
+       lsio_pwm2: pwm@5d020000 {
+               compatible = "fsl,imx27-pwm";
+               reg = <0x5d020000 0x10000>;
+               clock-names = "ipg", "per";
+               clocks = <&pwm2_lpcg 4>,
+                        <&pwm2_lpcg 1>;
+               assigned-clocks = <&clk IMX_SC_R_PWM_2 IMX_SC_PM_CLK_PER>;
+               assigned-clock-rates = <24000000>;
+               #pwm-cells = <2>;
+               status = "disabled";
+       };
+
+       lsio_pwm3: pwm@5d030000 {
+               compatible = "fsl,imx27-pwm";
+               reg = <0x5d030000 0x10000>;
+               clock-names = "ipg", "per";
+               clocks = <&pwm3_lpcg 4>,
+                        <&pwm3_lpcg 1>;
+               assigned-clocks = <&clk IMX_SC_R_PWM_3 IMX_SC_PM_CLK_PER>;
+               assigned-clock-rates = <24000000>;
+               #pwm-cells = <2>;
+               status = "disabled";
+       };
+
        lsio_gpio0: gpio@5d080000 {
                reg = <0x5d080000 0x10000>;
                interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;