ring->pipe ? (0x40 * ring->pipe - 0xc80) : 0);
 }
 
+static void jpeg_v4_0_3_ring_emit_hdp_flush(struct amdgpu_ring *ring)
+{
+       /* JPEG engine access for HDP flush doesn't work when RRMT is enabled.
+        * This is a workaround to avoid any HDP flush through JPEG ring.
+        */
+}
+
 /**
  * jpeg_v4_0_3_dec_ring_set_wptr - set write pointer
  *
        .emit_ib = jpeg_v4_0_3_dec_ring_emit_ib,
        .emit_fence = jpeg_v4_0_3_dec_ring_emit_fence,
        .emit_vm_flush = jpeg_v4_0_3_dec_ring_emit_vm_flush,
+       .emit_hdp_flush = jpeg_v4_0_3_ring_emit_hdp_flush,
        .test_ring = amdgpu_jpeg_dec_ring_test_ring,
        .test_ib = amdgpu_jpeg_dec_ring_test_ib,
        .insert_nop = jpeg_v4_0_3_dec_ring_nop,