clk: renesas: r9a09g057: Add clock and reset entries for I3C

Add module clock entries for the I3C controller on the RZ/V2H(P)
(R9A09G057) SoC.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://patch.msgid.link/20250904155507.245744-2-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

diff --git a/drivers/clk/renesas/r9a09g057-cpg.c b/drivers/clk/renesas/r9a09g057-cpg.c
index f7de69a93de148c15b2b37e14f726c43010fdcec..c2b5d04ed92ee5118615ae122ff7d2e0b62916cd 100644 (file)
--- a/drivers/clk/renesas/r9a09g057-cpg.c
+++ b/drivers/clk/renesas/r9a09g057-cpg.c
@@ -260,6 +260,12 @@ static const struct rzv2h_mod_clk r9a09g057_mod_clks[] __initconst = {
                                                BUS_MSTOP(11, BIT(2))),
        DEF_MOD("scif_0_clk_pck",               CLK_PLLCM33_DIV16, 8, 15, 4, 15,
                                                BUS_MSTOP(3, BIT(14))),
+       DEF_MOD("i3c_0_pclkrw",                 CLK_PLLCLN_DIV16, 9, 0, 4, 16,
+                                               BUS_MSTOP(10, BIT(15))),
+       DEF_MOD("i3c_0_pclk",                   CLK_PLLCLN_DIV16, 9, 1, 4, 17,
+                                               BUS_MSTOP(10, BIT(15))),
+       DEF_MOD("i3c_0_tclk",                   CLK_PLLCLN_DIV8, 9, 2, 4, 18,
+                                               BUS_MSTOP(10, BIT(15))),
        DEF_MOD("riic_8_ckm",                   CLK_PLLCM33_DIV16, 9, 3, 4, 19,
                                                BUS_MSTOP(3, BIT(13))),
        DEF_MOD("riic_0_ckm",                   CLK_PLLCLN_DIV16, 9, 4, 4, 20,
@@ -403,6 +409,8 @@ static const struct rzv2h_reset r9a09g057_resets[] __initconst = {
        DEF_RST(7, 15, 3, 16),          /* RSPI_2_PRESETN */
        DEF_RST(8, 0, 3, 17),           /* RSPI_2_TRESETN */
        DEF_RST(9, 5, 4, 6),            /* SCIF_0_RST_SYSTEM_N */
+       DEF_RST(9, 6, 4, 7),            /* I3C_0_PRESETN */
+       DEF_RST(9, 7, 4, 8),            /* I3C_0_TRESETN */
        DEF_RST(9, 8, 4, 9),            /* RIIC_0_MRST */
        DEF_RST(9, 9, 4, 10),           /* RIIC_1_MRST */
        DEF_RST(9, 10, 4, 11),          /* RIIC_2_MRST */