};
#define ISA_EXT_DATA_ENTRY(_name, _min_ver, _prop) \
- {#_name, _min_ver, offsetof(struct RISCVCPUConfig, _prop)}
+ {#_name, _min_ver, CPU_CFG_OFFSET(_prop)}
/*
* From vector_helper.c
const char *riscv_get_misa_ext_name(uint32_t bit);
const char *riscv_get_misa_ext_description(uint32_t bit);
+#define CPU_CFG_OFFSET(_prop) offsetof(struct RISCVCPUConfig, _prop)
+
/* Privileged specification version */
enum {
PRIV_VERSION_1_10_0 = 0,
}
}
-#define CPUCFG(_prop) offsetof(struct RISCVCPUConfig, _prop)
-
#define KVM_EXT_CFG(_name, _prop, _reg_id) \
- {.name = _name, .offset = CPUCFG(_prop), \
+ {.name = _name, .offset = CPU_CFG_OFFSET(_prop), \
.kvm_reg_id = _reg_id}
static KVMCPUConfig kvm_multi_ext_cfgs[] = {
static KVMCPUConfig kvm_cbom_blocksize = {
.name = "cbom_blocksize",
- .offset = CPUCFG(cbom_blocksize),
+ .offset = CPU_CFG_OFFSET(cbom_blocksize),
.kvm_reg_id = KVM_REG_RISCV_CONFIG_REG(zicbom_block_size)
};
static KVMCPUConfig kvm_cboz_blocksize = {
.name = "cboz_blocksize",
- .offset = CPUCFG(cboz_blocksize),
+ .offset = CPU_CFG_OFFSET(cboz_blocksize),
.kvm_reg_id = KVM_REG_RISCV_CONFIG_REG(zicboz_block_size)
};