if (hsotg->clk) {
                ret = clk_prepare_enable(hsotg->clk);
                if (ret)
-                       return ret;
+                       goto err_dis_reg;
        }
 
        if (hsotg->uphy) {
                ret = hsotg->plat->phy_init(pdev, hsotg->plat->phy_type);
        } else {
                ret = phy_init(hsotg->phy);
-               if (ret == 0)
+               if (ret == 0) {
                        ret = phy_power_on(hsotg->phy);
+                       if (ret)
+                               phy_exit(hsotg->phy);
+               }
        }
 
+       if (ret)
+               goto err_dis_clk;
+
+       return 0;
+
+err_dis_clk:
+       if (hsotg->clk)
+               clk_disable_unprepare(hsotg->clk);
+
+err_dis_reg:
+       regulator_bulk_disable(ARRAY_SIZE(hsotg->supplies), hsotg->supplies);
+
        return ret;
 }