msm: iommu: Increase maximum MID size to 5 bits

On msm8x60, the MID field on the AXI connection to the
IOMMU can be up to five bits wide. Thus, allow the IOMMU
context platform data to map up to 32 MIDs.

Signed-off-by: Stepan Moskovchenko <stepanm@codeaurora.org>
Signed-off-by: Daniel Walker <dwalker@codeaurora.org>

diff --git a/arch/arm/mach-msm/include/mach/iommu.h b/arch/arm/mach-msm/include/mach/iommu.h
index 218ef5732a24162217c56c99263655bbeca85d4b..17fc79fc8bc2c33101babd0f0d164f2436a47bb2 100644 (file)
--- a/arch/arm/mach-msm/include/mach/iommu.h
+++ b/arch/arm/mach-msm/include/mach/iommu.h
@@ -26,7 +26,7 @@
  * be present. These mappings are typically determined at design time and are
  * not expected to change at run time.
  */
-#define MAX_NUM_MIDS   16
+#define MAX_NUM_MIDS   32
 
 /**
  * struct msm_iommu_dev - a single IOMMU hardware instance