RDSPROTO Patch by Marius Gröger, 10 Apr 2001 12:05:28

diff --git a/include/config_rsdproto.h b/include/config_rsdproto.h
index e84b6fb0c8efd74aa4b32423429fa5b61d4e5b36..fb6b9ba49062a2ab1e198cbeae53b302f8e320e1 100644 (file)
--- a/include/config_rsdproto.h
+++ b/include/config_rsdproto.h
@@ -73,12 +73,12 @@
 #define CONFIG_ENV_OVERWRITE
 
 /* enable I2C */
-#define CONFIG_I2C          1
+#define CONFIG_I2C             1
 
 /* system clock rate (CLKIN) - equal to the 60x and local bus speed */
 #define CONFIG_8260_CLKIN      50000000        /* in Hz */
 
-#define CONFIG_BAUDRATE                9600
+#define CONFIG_BAUDRATE                115200
 
 #define CONFIG_COMMANDS                (CONFIG_CMD_DFL & ~CFG_CMD_KGDB)
 
@@ -94,6 +94,14 @@
 #include <cmd_confdefs.h>
 
 #define CONFIG_BOOTDELAY       5
+#define CONFIG_BOOTARGS        "devfs=mount root=ramfs"
+#define CONFIG_ETHADDR         08:00:3e:26:0a:5a
+#define CONFIG_NETMASK          255.255.0.0
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE   230400          /* speed to run kgdb serial port */
+#define CONFIG_KGDB_SER_INDEX  2               /* which serial port to use */
+#endif
 
 /*
  * Miscellaneous configurable options
@@ -106,7 +114,7 @@
 #define        CFG_CBSIZE              256             /* Console I/O Buffer Size      */
 #endif
 #define        CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define        CFG_MAXARGS             8               /* max number of command args   */
+#define        CFG_MAXARGS             16              /* max number of command args   */
 #define CFG_BARGSIZE           CFG_CBSIZE      /* Boot Argument Buffer Size    */
 
 #define CFG_MEMTEST_START      0x00400000      /* memtest works on     */
@@ -136,17 +144,20 @@
 #define PHYS_SDRAM_LOCAL       0x40000000 /* SDRAM (Local Bus) */
 #define PHYS_SDRAM_LOCAL_SIZE  0x04000000 /* 64 MB */
 
-#define PHYS_DPRAM_PCI         0x04000000 /* DPRAM PPC/PCI */
+#define PHYS_DPRAM_PCI         0xE8000000 /* DPRAM PPC/PCI */
 #define PHYS_DPRAM_PCI_SIZE    0x00020000 /* 128 KB */
 
-#define PHYS_DPRAM_PCI_SEM     0x04020000 /* DPRAM PPC/PCI Semaphore */
-#define PHYS_DPRAM_PCI_SEM_SIZE        0x00000001 /* 1 Byte */
+//#define PHYS_DPRAM_PCI_SEM   0x04020000 /* DPRAM PPC/PCI Semaphore */
+//#define PHYS_DPRAM_PCI_SEM_SIZE      0x00000001 /* 1 Byte */
 
-#define PHYS_DPRAM_SHARC               0x04100000 /* DPRAM PPC/Sharc */
+#define PHYS_DPRAM_SHARC               0xE8100000 /* DPRAM PPC/Sharc */
 #define PHYS_DPRAM_SHARC_SIZE  0x00040000 /* 256 KB */
 
-#define PHYS_DPRAM_SHARC_SEM   0x04140000 /* DPRAM PPC/Sharc Semaphore */
-#define PHYS_DPRAM_SHARC_SEM_SIZE 0x00000001 /* 1 Byte */
+//#define PHYS_DPRAM_SHARC_SEM 0x04140000 /* DPRAM PPC/Sharc Semaphore */
+//#define PHYS_DPRAM_SHARC_SEM_SIZE 0x00000001 /* 1 Byte */
+
+#define PHYS_VIRTEX_REGISTER    0xE8300000 /* FPGA implemented register */
+#define PHYS_VIRTEX_REGISTER_SIZE 0x00000100 
 
 #define PHYS_USB               0x04200000 /* USB Controller (60x Bus) */
 #define PHYS_USB_SIZE          0x00000002 /* 2 Bytes */
@@ -338,24 +349,18 @@
 #define CFG_PSDMR      0x494D2452
 #define CFG_LSDMR      0x49492552
 
+/* Flash */
 #define CFG_BR0_PRELIM (PHYS_FLASH | BRx_V)
 #define CFG_OR0_PRELIM (P2SZ_TO_AM(PHYS_FLASH_SIZE) | \
                         ORxG_BCTLD | \
                         ORxG_SCY_5_CLK)
 
+/* DPRAM to the PCI BUS on the protocol board */
 #define CFG_BR1_PRELIM (PHYS_DPRAM_PCI | BRx_V)
 #define CFG_OR1_PRELIM (P2SZ_TO_AM(PHYS_DPRAM_PCI_SIZE) | \
                         ORxG_ACS_DIV4)
 
-#define CFG_BR4_PRELIM (PHYS_SDRAM_LOCAL | BRx_PS_32 | BRx_MS_SDRAM_L | BRx_V)
-#define CFG_OR4_PRELIM (ORxS_SIZE_TO_AM(PHYS_SDRAM_LOCAL_SIZE) | \
-                        ORxS_BPD_4 | \
-                        ORxS_ROWST_PBI1_A4 | \
-                        ORxS_NUMR_13)
-
-#define CFG_BR3_PRELIM  0
-#define CFG_OR3_PRELIM  0
-
+/* 60x Bus SDRAM */
 #define CFG_BR2_PRELIM (PHYS_SDRAM_60X | BRx_MS_SDRAM_P | BRx_V)
 #define CFG_OR2_PRELIM (ORxS_SIZE_TO_AM(PHYS_SDRAM_60X_SIZE) | \
                         ORxS_BPD_4 | \
@@ -363,6 +368,21 @@
                         ORxS_NUMR_13 | \
                         ORxS_IBID)
 
+/* Virtex-FPGA - Register */
+#define CFG_BR3_PRELIM  (PHYS_VIRTEX_REGISTER | BRx_V)
+#define CFG_OR3_PRELIM  (ORxS_SIZE_TO_AM(PHYS_VIRTEX_REGISTER_SIZE) | \
+                         ORxG_SCY_1_CLK | \
+                         ORxG_ACS_DIV2 | \
+                         ORxG_CSNT )
+
+/* local bus SDRAM */
+#define CFG_BR4_PRELIM (PHYS_SDRAM_LOCAL | BRx_PS_32 | BRx_MS_SDRAM_L | BRx_V)
+#define CFG_OR4_PRELIM (ORxS_SIZE_TO_AM(PHYS_SDRAM_LOCAL_SIZE) | \
+                        ORxS_BPD_4 | \
+                        ORxS_ROWST_PBI1_A4 | \
+                        ORxS_NUMR_13)
+
+/* DPRAM to the Sharc-Bus on the protocol board */
 #define CFG_BR5_PRELIM (PHYS_DPRAM_SHARC | BRx_V)
 #define CFG_OR5_PRELIM (P2SZ_TO_AM(PHYS_DPRAM_SHARC_SIZE) | \
                         ORxG_ACS_DIV4)