break;
        case RF90_PATH_B:
                for (i = 0; i < RTL8192E_RADIO_B_ARR_LEN; i += 2) {
-                       if (Rtl819XRadioB_Array[i] == 0xfe) {
+                       if (RTL8192E_RADIO_B_ARR[i] == 0xfe) {
                                msleep(100);
                                continue;
                        }
-                       rtl92e_set_rf_reg(dev, eRFPath, Rtl819XRadioB_Array[i],
+                       rtl92e_set_rf_reg(dev, eRFPath, RTL8192E_RADIO_B_ARR[i],
                                          bMask12Bits,
-                                         Rtl819XRadioB_Array[i+1]);
+                                         RTL8192E_RADIO_B_ARR[i + 1]);
 
                }
                break;
 
 
 #define MAX_DOZE_WAITING_TIMES_9x 64
 
-#define Rtl819XRadioB_Array                    Rtl8192PciERadioB_Array
 #define Rtl819XAGCTAB_Array                    Rtl8192PciEAGCTAB_Array
 #define Rtl819XPHY_REG_1T2RArray               Rtl8192PciEPHY_REG_1T2RArray
 
 
        0x007, 0x00000700,
 };
 
-u32 Rtl8192PciERadioB_Array[RTL8192E_RADIO_B_ARR_LEN] = {
+u32 RTL8192E_RADIO_B_ARR[RTL8192E_RADIO_B_ARR_LEN] = {
        0x019, 0x00000003,
        0x000, 0x000000bf,
        0x001, 0x000006e0,
 
 #define RTL8192E_RADIO_A_ARR_LEN 246
 extern u32 RTL8192E_RADIO_A_ARR[RTL8192E_RADIO_A_ARR_LEN];
 #define RTL8192E_RADIO_B_ARR_LEN 78
-extern u32 Rtl8192PciERadioB_Array[RTL8192E_RADIO_B_ARR_LEN];
+extern u32 RTL8192E_RADIO_B_ARR[RTL8192E_RADIO_B_ARR_LEN];
 #define RTL8192E_MACPHY_ARR_LEN 18
 extern u32 RTL8192E_MACPHY_ARR[RTL8192E_MACPHY_ARR_LEN];
 #define RTL8192E_MACPHY_ARR_PG_LEN 30