]> www.infradead.org Git - users/mchehab/rasdaemon.git/commitdiff
ras-mce-handler: Add support for Hygon Dhyana family 18h processor
authorPu Wen <puwen@hygon.cn>
Thu, 23 May 2019 13:00:22 +0000 (21:00 +0800)
committerMauro Carvalho Chehab <mchehab+samsung@kernel.org>
Mon, 24 Jun 2019 12:40:55 +0000 (09:40 -0300)
The Hygon Dhyana family 18h processor is derived from AMD family 17h.
The Hygon Dhyana support to Linux is already accepted upstream[1].

Add Hygon Dhyana support to mce handler of rasdaemon in order to handle
MCE events on Hygon Dhyana platforms.

Reference:
[1] https://git.kernel.org/tip/fec98069fb72fb656304a3e52265e0c2fc9adf87

Signed-off-by: Pu Wen <puwen@hygon.cn>
Signed-off-by: Mauro Carvalho Chehab <mchehab+samsung@kernel.org>
ras-mce-handler.c
ras-mce-handler.h

index 7ab233508ebac2fd86f8cc3eb2d8d08d895acc05..fd3ef3bc455b45ecb70b6b259a6dea82f72b4de0 100644 (file)
@@ -55,7 +55,8 @@ static char *cputype_name[] = {
        [CPU_KNIGHTS_LANDING] = "Knights Landing",
        [CPU_KNIGHTS_MILL] = "Knights Mill",
        [CPU_SKYLAKE_XEON] = "Skylake server",
-       [CPU_NAPLES] = "AMD Family 17h Zen1"
+       [CPU_NAPLES] = "AMD Family 17h Zen1",
+       [CPU_DHYANA] = "Hygon Family 18h Moksha"
 };
 
 static enum cputype select_intel_cputype(struct ras_events *ras)
@@ -200,6 +201,11 @@ static int detect_cpu(struct ras_events *ras)
                        ret = EINVAL;
                }
                goto ret;
+       } else if (!strcmp(mce->vendor,"HygonGenuine")) {
+               if (mce->family == 24) {
+                       mce->cputype = CPU_DHYANA;
+               }
+               goto ret;
        } else if (!strcmp(mce->vendor,"GenuineIntel")) {
                mce->cputype = select_intel_cputype(ras);
        } else {
@@ -436,6 +442,7 @@ int ras_mce_event_handler(struct trace_seq *s,
                rc = parse_amd_k8_event(ras, &e);
                break;
        case CPU_NAPLES:
+       case CPU_DHYANA:
                rc = parse_amd_smca_event(ras, &e);
                break;
        default:                        /* All other CPU types are Intel */
index 8aaecd1e4d1bdcd84b9783d651faa916fa831b05..94395eb51a56eace581b4a21ad9bfa5dd86bbc04 100644 (file)
@@ -51,6 +51,7 @@ enum cputype {
        CPU_KNIGHTS_MILL,
        CPU_SKYLAKE_XEON,
        CPU_NAPLES,
+       CPU_DHYANA,
 };
 
 struct mce_event {