drm/amdgpu/VCN2: put IB internal registers offset to structure

So the ring functions can be shared with different VCN versions
with different internal registers offsets

Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
index 99f14fcc1460550c66e0bf7dfdfedcfc8b297723..bfd8c3cea13ae54c1c24d49ba5d14ff010648e63 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
@@ -145,6 +145,12 @@ struct amdgpu_vcn_reg{
        unsigned        data1;
        unsigned        cmd;
        unsigned        nop;
+       unsigned        context_id;
+       unsigned        ib_vmid;
+       unsigned        ib_bar_low;
+       unsigned        ib_bar_high;
+       unsigned        ib_size;
+       unsigned        gp_scratch8;
        unsigned        scratch9;
        unsigned        jpeg_pitch;
 };

diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
index c701868dd57fd9cd396ac2f2884c3577a12d62cf..9bb29cd3aa50a37a40116d5fd916b0989f92dded 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
@@ -166,6 +166,13 @@ static int vcn_v2_0_sw_init(void *handle)
        if (r)
                return r;
 
+       adev->vcn.internal.context_id = mmUVD_CONTEXT_ID_INTERNAL_OFFSET;
+       adev->vcn.internal.ib_vmid = mmUVD_LMI_RBC_IB_VMID_INTERNAL_OFFSET;
+       adev->vcn.internal.ib_bar_low = mmUVD_LMI_RBC_IB_64BIT_BAR_LOW_INTERNAL_OFFSET;
+       adev->vcn.internal.ib_bar_high = mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH_INTERNAL_OFFSET;
+       adev->vcn.internal.ib_size = mmUVD_RBC_IB_SIZE_INTERNAL_OFFSET;
+       adev->vcn.internal.gp_scratch8 = mmUVD_GP_SCRATCH8_INTERNAL_OFFSET;
+
        adev->vcn.internal.scratch9 = mmUVD_SCRATCH9_INTERNAL_OFFSET;
        adev->vcn.external.scratch9 = SOC15_REG_OFFSET(UVD, 0, mmUVD_SCRATCH9);
        adev->vcn.internal.data0 = mmUVD_GPCOM_VCPU_DATA0_INTERNAL_OFFSET;
@@ -1485,9 +1492,11 @@ static void vcn_v2_0_dec_ring_set_wptr(struct amdgpu_ring *ring)
  */
 static void vcn_v2_0_dec_ring_insert_start(struct amdgpu_ring *ring)
 {
-       amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0_INTERNAL_OFFSET, 0));
+       struct amdgpu_device *adev = ring->adev;
+
+       amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.data0, 0));
        amdgpu_ring_write(ring, 0);
-       amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD_INTERNAL_OFFSET, 0));
+       amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.cmd, 0));
        amdgpu_ring_write(ring, VCN_DEC_CMD_PACKET_START << 1);
 }
 
@@ -1500,7 +1509,9 @@ static void vcn_v2_0_dec_ring_insert_start(struct amdgpu_ring *ring)
  */
 static void vcn_v2_0_dec_ring_insert_end(struct amdgpu_ring *ring)
 {
-       amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD_INTERNAL_OFFSET, 0));
+       struct amdgpu_device *adev = ring->adev;
+
+       amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.cmd, 0));
        amdgpu_ring_write(ring, VCN_DEC_CMD_PACKET_END << 1);
 }
 
@@ -1513,12 +1524,13 @@ static void vcn_v2_0_dec_ring_insert_end(struct amdgpu_ring *ring)
  */
 static void vcn_v2_0_dec_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count)
 {
+       struct amdgpu_device *adev = ring->adev;
        int i;
 
        WARN_ON(ring->wptr % 2 || count % 2);
 
        for (i = 0; i < count / 2; i++) {
-               amdgpu_ring_write(ring, PACKET0(mmUVD_NO_OP_INTERNAL_OFFSET, 0));
+               amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.nop, 0));
                amdgpu_ring_write(ring, 0);
        }
 }
@@ -1534,27 +1546,28 @@ static void vcn_v2_0_dec_ring_insert_nop(struct amdgpu_ring *ring, uint32_t coun
 static void vcn_v2_0_dec_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
                                     unsigned flags)
 {
-       WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT);
+       struct amdgpu_device *adev = ring->adev;
 
-       amdgpu_ring_write(ring, PACKET0(mmUVD_CONTEXT_ID_INTERNAL_OFFSET, 0));
+       WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT);
+       amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.context_id, 0));
        amdgpu_ring_write(ring, seq);
 
-       amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0_INTERNAL_OFFSET, 0));
+       amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.data0, 0));
        amdgpu_ring_write(ring, addr & 0xffffffff);
 
-       amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1_INTERNAL_OFFSET, 0));
+       amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.data1, 0));
        amdgpu_ring_write(ring, upper_32_bits(addr) & 0xff);
 
-       amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD_INTERNAL_OFFSET, 0));
+       amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.cmd, 0));
        amdgpu_ring_write(ring, VCN_DEC_CMD_FENCE << 1);
 
-       amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0_INTERNAL_OFFSET, 0));
+       amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.data0, 0));
        amdgpu_ring_write(ring, 0);
 
-       amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1_INTERNAL_OFFSET, 0));
+       amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.data1, 0));
        amdgpu_ring_write(ring, 0);
 
-       amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD_INTERNAL_OFFSET, 0));
+       amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.cmd, 0));
 
        amdgpu_ring_write(ring, VCN_DEC_CMD_TRAP << 1);
 }
@@ -1572,16 +1585,17 @@ static void vcn_v2_0_dec_ring_emit_ib(struct amdgpu_ring *ring,
                                      struct amdgpu_ib *ib,
                                      uint32_t flags)
 {
+       struct amdgpu_device *adev = ring->adev;
        unsigned vmid = AMDGPU_JOB_GET_VMID(job);
 
-       amdgpu_ring_write(ring, PACKET0(mmUVD_LMI_RBC_IB_VMID_INTERNAL_OFFSET, 0));
+       amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.ib_vmid, 0));
        amdgpu_ring_write(ring, vmid);
 
-       amdgpu_ring_write(ring, PACKET0(mmUVD_LMI_RBC_IB_64BIT_BAR_LOW_INTERNAL_OFFSET, 0));
+       amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.ib_bar_low, 0));
        amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr));
-       amdgpu_ring_write(ring, PACKET0(mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH_INTERNAL_OFFSET, 0));
+       amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.ib_bar_high, 0));
        amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
-       amdgpu_ring_write(ring, PACKET0(mmUVD_RBC_IB_SIZE_INTERNAL_OFFSET, 0));
+       amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.ib_size, 0));
        amdgpu_ring_write(ring, ib->length_dw);
 }
 
@@ -1589,16 +1603,18 @@ static void vcn_v2_0_dec_ring_emit_reg_wait(struct amdgpu_ring *ring,
                                            uint32_t reg, uint32_t val,
                                            uint32_t mask)
 {
-       amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0_INTERNAL_OFFSET, 0));
+       struct amdgpu_device *adev = ring->adev;
+
+       amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.data0, 0));
        amdgpu_ring_write(ring, reg << 2);
 
-       amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1_INTERNAL_OFFSET, 0));
+       amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.data1, 0));
        amdgpu_ring_write(ring, val);
 
-       amdgpu_ring_write(ring, PACKET0(mmUVD_GP_SCRATCH8_INTERNAL_OFFSET, 0));
+       amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.gp_scratch8, 0));
        amdgpu_ring_write(ring, mask);
 
-       amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD_INTERNAL_OFFSET, 0));
+       amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.cmd, 0));
 
        amdgpu_ring_write(ring, VCN_DEC_CMD_REG_READ_COND_WAIT << 1);
 }
@@ -1621,13 +1637,15 @@ static void vcn_v2_0_dec_ring_emit_vm_flush(struct amdgpu_ring *ring,
 static void vcn_v2_0_dec_ring_emit_wreg(struct amdgpu_ring *ring,
                                        uint32_t reg, uint32_t val)
 {
-       amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0_INTERNAL_OFFSET, 0));
+       struct amdgpu_device *adev = ring->adev;
+
+       amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.data0, 0));
        amdgpu_ring_write(ring, reg << 2);
 
-       amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1_INTERNAL_OFFSET, 0));
+       amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.data1, 0));
        amdgpu_ring_write(ring, val);
 
-       amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD_INTERNAL_OFFSET, 0));
+       amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.cmd, 0));
 
        amdgpu_ring_write(ring, VCN_DEC_CMD_WRITE_REG << 1);
 }