drm/i915/adl_p: Add PLL Support

The clocks in ALD_P is similar to that of TGL.
The combo PLLs  use the same DPLL0, DPLL1 and TBT_PLL.

This patch adds the helper function intel_mg_pll_enable_reg()
which is similar to intel_combo_pll_enable_reg() for being lookup
place for PLL_ENABLE register in combo phy cases.

Bspec: 55409,55316
Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Clinton Taylor <clinton.a.taylor@intel.com>
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Cc: José Roberto de Souza <jose.souza@intel.com>
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
Signed-off-by: Clinton Taylor <Clinton.A.Taylor@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Clint Taylor <Clinton.A.Taylor@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210519000625.3184321-15-lucas.demarchi@intel.com

diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index 18bfe8d09277400ea512c8cc2ccc7ddbd4512a46..71ac5767004325e9a8a86aa75e79f2ec53bee1d7 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -149,6 +149,16 @@ void assert_shared_dpll(struct drm_i915_private *dev_priv,
                        pll->info->name, onoff(state), onoff(cur_state));
 }
 
+static enum tc_port icl_pll_id_to_tc_port(enum intel_dpll_id id)
+{
+       return TC_PORT_1 + id - DPLL_ID_ICL_MGPLL1;
+}
+
+enum intel_dpll_id icl_tc_port_to_pll_id(enum tc_port tc_port)
+{
+       return tc_port - TC_PORT_1 + DPLL_ID_ICL_MGPLL1;
+}
+
 static i915_reg_t
 intel_combo_pll_enable_reg(struct drm_i915_private *i915,
                           struct intel_shared_dpll *pll)
@@ -161,6 +171,19 @@ intel_combo_pll_enable_reg(struct drm_i915_private *i915,
        return CNL_DPLL_ENABLE(pll->info->id);
 }
 
+static i915_reg_t
+intel_tc_pll_enable_reg(struct drm_i915_private *i915,
+                       struct intel_shared_dpll *pll)
+{
+       const enum intel_dpll_id id = pll->info->id;
+       enum tc_port tc_port = icl_pll_id_to_tc_port(id);
+
+       if (IS_ALDERLAKE_P(i915))
+               return ADLP_PORTTC_PLL_ENABLE(tc_port);
+
+       return MG_PLL_ENABLE(tc_port);
+}
+
 /**
  * intel_prepare_shared_dpll - call a dpll's prepare hook
  * @crtc_state: CRTC, and its state, which has a shared dpll
@@ -3120,16 +3143,6 @@ static void icl_calc_dpll_state(struct drm_i915_private *i915,
                pll_state->cfgcr1 |= DPLL_CFGCR1_CENTRAL_FREQ_8400;
 }
 
-static enum tc_port icl_pll_id_to_tc_port(enum intel_dpll_id id)
-{
-       return id - DPLL_ID_ICL_MGPLL1;
-}
-
-enum intel_dpll_id icl_tc_port_to_pll_id(enum tc_port tc_port)
-{
-       return tc_port + DPLL_ID_ICL_MGPLL1;
-}
-
 static bool icl_mg_pll_find_divisors(int clock_khz, bool is_dp, bool use_ssc,
                                     u32 *target_dco_khz,
                                     struct intel_dpll_hw_state *state,
@@ -3728,12 +3741,14 @@ static bool mg_pll_get_hw_state(struct drm_i915_private *dev_priv,
        bool ret = false;
        u32 val;
 
+       i915_reg_t enable_reg = intel_tc_pll_enable_reg(dev_priv, pll);
+
        wakeref = intel_display_power_get_if_enabled(dev_priv,
                                                     POWER_DOMAIN_DISPLAY_CORE);
        if (!wakeref)
                return false;
 
-       val = intel_de_read(dev_priv, MG_PLL_ENABLE(tc_port));
+       val = intel_de_read(dev_priv, enable_reg);
        if (!(val & PLL_ENABLE))
                goto out;
 
@@ -3797,7 +3812,7 @@ static bool dkl_pll_get_hw_state(struct drm_i915_private *dev_priv,
        if (!wakeref)
                return false;
 
-       val = intel_de_read(dev_priv, MG_PLL_ENABLE(tc_port));
+       val = intel_de_read(dev_priv, intel_tc_pll_enable_reg(dev_priv, pll));
        if (!(val & PLL_ENABLE))
                goto out;
 
@@ -4169,8 +4184,7 @@ static void tbt_pll_enable(struct drm_i915_private *dev_priv,
 static void mg_pll_enable(struct drm_i915_private *dev_priv,
                          struct intel_shared_dpll *pll)
 {
-       i915_reg_t enable_reg =
-               MG_PLL_ENABLE(icl_pll_id_to_tc_port(pll->info->id));
+       i915_reg_t enable_reg = intel_tc_pll_enable_reg(dev_priv, pll);
 
        icl_pll_power_enable(dev_priv, pll, enable_reg);
 
@@ -4249,8 +4263,7 @@ static void tbt_pll_disable(struct drm_i915_private *dev_priv,
 static void mg_pll_disable(struct drm_i915_private *dev_priv,
                           struct intel_shared_dpll *pll)
 {
-       i915_reg_t enable_reg =
-               MG_PLL_ENABLE(icl_pll_id_to_tc_port(pll->info->id));
+       i915_reg_t enable_reg = intel_tc_pll_enable_reg(dev_priv, pll);
 
        icl_pll_disable(dev_priv, pll, enable_reg);
 }
@@ -4416,6 +4429,26 @@ static const struct intel_dpll_mgr adls_pll_mgr = {
        .dump_hw_state = icl_dump_hw_state,
 };
 
+static const struct dpll_info adlp_plls[] = {
+       { "DPLL 0", &combo_pll_funcs, DPLL_ID_ICL_DPLL0,  0 },
+       { "DPLL 1", &combo_pll_funcs, DPLL_ID_ICL_DPLL1,  0 },
+       { "TBT PLL",  &tbt_pll_funcs, DPLL_ID_ICL_TBTPLL, 0 },
+       { "TC PLL 1", &dkl_pll_funcs, DPLL_ID_ICL_MGPLL1, 0 },
+       { "TC PLL 2", &dkl_pll_funcs, DPLL_ID_ICL_MGPLL2, 0 },
+       { "TC PLL 3", &dkl_pll_funcs, DPLL_ID_ICL_MGPLL3, 0 },
+       { "TC PLL 4", &dkl_pll_funcs, DPLL_ID_ICL_MGPLL4, 0 },
+       { },
+};
+
+static const struct intel_dpll_mgr adlp_pll_mgr = {
+       .dpll_info = adlp_plls,
+       .get_dplls = icl_get_dplls,
+       .put_dplls = icl_put_dplls,
+       .update_active_dpll = icl_update_active_dpll,
+       .update_ref_clks = icl_update_dpll_ref_clks,
+       .dump_hw_state = icl_dump_hw_state,
+};
+
 /**
  * intel_shared_dpll_init - Initialize shared DPLLs
  * @dev: drm device
@@ -4429,7 +4462,9 @@ void intel_shared_dpll_init(struct drm_device *dev)
        const struct dpll_info *dpll_info;
        int i;
 
-       if (IS_ALDERLAKE_S(dev_priv))
+       if (IS_ALDERLAKE_P(dev_priv))
+               dpll_mgr = &adlp_pll_mgr;
+       else if (IS_ALDERLAKE_S(dev_priv))
                dpll_mgr = &adls_pll_mgr;
        else if (IS_DG1(dev_priv))
                dpll_mgr = &dg1_pll_mgr;

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 7d8c11b7ff3ee13b55a2be7e59785b3cd57c9455..90c91672836f85c55e5d69ce22ddfc31d10446bb 100644 (file)
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -10531,6 +10531,14 @@ enum skl_power_gate {
 #define DG1_DPLL_ENABLE(pll)    _MMIO_PLL3(pll, DPLL0_ENABLE, DPLL1_ENABLE, \
                                           _MG_PLL1_ENABLE, _MG_PLL2_ENABLE)
 
+/* ADL-P Type C PLL */
+#define PORTTC1_PLL_ENABLE     0x46038
+#define PORTTC2_PLL_ENABLE     0x46040
+
+#define ADLP_PORTTC_PLL_ENABLE(tc_port)                _MMIO_PORT((tc_port), \
+                                                           PORTTC1_PLL_ENABLE, \
+                                                           PORTTC2_PLL_ENABLE)
+
 #define _MG_REFCLKIN_CTL_PORT1                         0x16892C
 #define _MG_REFCLKIN_CTL_PORT2                         0x16992C
 #define _MG_REFCLKIN_CTL_PORT3                         0x16A92C