arm64: dts: qcom: ipq5018: Enable PCIe

Enable the PCIe controller and PHY nodes for RDP 432-c2.

Signed-off-by: Nitheesh Sekar <quic_nsekar@quicinc.com>
Signed-off-by: Sricharan Ramabadhran <quic_srichara@quicinc.com>
Acked-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Signed-off-by: George Moussalem <george.moussalem@outlook.com>
Link: https://lore.kernel.org/r/20250514-ipq5018-pcie-v10-2-5b42a8eff7ea@outlook.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

diff --git a/arch/arm64/boot/dts/qcom/ipq5018-rdp432-c2.dts b/arch/arm64/boot/dts/qcom/ipq5018-rdp432-c2.dts
index 8460b538eb6a3e2d6b971bd9637309809e0c0f0c..43def95e9275258041e7522ba4098a3767be3df1 100644 (file)
--- a/arch/arm64/boot/dts/qcom/ipq5018-rdp432-c2.dts
+++ b/arch/arm64/boot/dts/qcom/ipq5018-rdp432-c2.dts
@@ -9,6 +9,8 @@
 
 #include "ipq5018.dtsi"
 
+#include <dt-bindings/gpio/gpio.h>
+
 / {
        model = "Qualcomm Technologies, Inc. IPQ5018/AP-RDP432.1-C2";
        compatible = "qcom,ipq5018-rdp432-c2", "qcom,ipq5018";
@@ -28,6 +30,20 @@
        status = "okay";
 };
 
+&pcie0 {
+       pinctrl-0 = <&pcie0_default>;
+       pinctrl-names = "default";
+
+       perst-gpios = <&tlmm 15 GPIO_ACTIVE_LOW>;
+       wake-gpios = <&tlmm 16 GPIO_ACTIVE_LOW>;
+
+       status = "okay";
+};
+
+&pcie0_phy {
+       status = "okay";
+};
+
 &sdhc_1 {
        pinctrl-0 = <&sdc_default_state>;
        pinctrl-names = "default";
@@ -43,6 +59,30 @@
 };
 
 &tlmm {
+       pcie0_default: pcie0-default-state {
+               clkreq-n-pins {
+                       pins = "gpio14";
+                       function = "pcie0_clk";
+                       drive-strength = <8>;
+                       bias-pull-up;
+               };
+
+               perst-n-pins {
+                       pins = "gpio15";
+                       function = "gpio";
+                       drive-strength = <8>;
+                       bias-pull-up;
+                       output-low;
+               };
+
+               wake-n-pins {
+                       pins = "gpio16";
+                       function = "pcie0_wake";
+                       drive-strength = <8>;
+                       bias-pull-up;
+               };
+       };
+
        sdc_default_state: sdc-default-state {
                clk-pins {
                        pins = "gpio9";