drm/amdgpu: add a BO metadata flag to disable write compression for Vulkan

Vulkan can't support DCC and Z/S compression on GFX12 without
WRITE_COMPRESS_DISABLE in this commit or a completely different DCC
interface.

AMDGPU_TILING_GFX12_SCANOUT is added because it's already used by userspace.

Cc: stable@vger.kernel.org # 6.12.x
Signed-off-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
index 817116e53d4402f9ac0d3d29d71e82711ba6c960..dce9323fb410c9da55abcca977778960048c51b7 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
@@ -119,9 +119,10 @@
  * - 3.57.0 - Compute tunneling on GFX10+
  * - 3.58.0 - Add GFX12 DCC support
  * - 3.59.0 - Cleared VRAM
+ * - 3.60.0 - Add AMDGPU_TILING_GFX12_DCC_WRITE_COMPRESS_DISABLE (Vulkan requirement)
  */
 #define KMS_DRIVER_MAJOR       3
-#define KMS_DRIVER_MINOR       59
+#define KMS_DRIVER_MINOR       60
 #define KMS_DRIVER_PATCHLEVEL  0
 
 /*

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
index ff286940ab430428cf53df722f3822b10c83c213..01ae2f88dec8c6a082b63e891c11bbc3ae0f23d2 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
@@ -309,7 +309,7 @@ int amdgpu_ttm_copy_mem_to_mem(struct amdgpu_device *adev,
        mutex_lock(&adev->mman.gtt_window_lock);
        while (src_mm.remaining) {
                uint64_t from, to, cur_size, tiling_flags;
-               uint32_t num_type, data_format, max_com;
+               uint32_t num_type, data_format, max_com, write_compress_disable;
                struct dma_fence *next;
 
                /* Never copy more than 256MiB at once to avoid a timeout */
@@ -340,9 +340,13 @@ int amdgpu_ttm_copy_mem_to_mem(struct amdgpu_device *adev,
                        max_com = AMDGPU_TILING_GET(tiling_flags, GFX12_DCC_MAX_COMPRESSED_BLOCK);
                        num_type = AMDGPU_TILING_GET(tiling_flags, GFX12_DCC_NUMBER_TYPE);
                        data_format = AMDGPU_TILING_GET(tiling_flags, GFX12_DCC_DATA_FORMAT);
+                       write_compress_disable =
+                               AMDGPU_TILING_GET(tiling_flags, GFX12_DCC_WRITE_COMPRESS_DISABLE);
                        copy_flags |= (AMDGPU_COPY_FLAGS_SET(MAX_COMPRESSED, max_com) |
                                       AMDGPU_COPY_FLAGS_SET(NUMBER_TYPE, num_type) |
-                                      AMDGPU_COPY_FLAGS_SET(DATA_FORMAT, data_format));
+                                      AMDGPU_COPY_FLAGS_SET(DATA_FORMAT, data_format) |
+                                      AMDGPU_COPY_FLAGS_SET(WRITE_COMPRESS_DISABLE,
+                                                            write_compress_disable));
                }
 
                r = amdgpu_copy_buffer(ring, from, to, cur_size, resv,

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h
index 461fb8090ae04083326c460f48f96d6ae1485f3b..208b7d1d8a277bd8463b836a7d3d0a49822325dc 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h
@@ -119,6 +119,8 @@ struct amdgpu_copy_mem {
 #define AMDGPU_COPY_FLAGS_NUMBER_TYPE_MASK             0x07
 #define AMDGPU_COPY_FLAGS_DATA_FORMAT_SHIFT            8
 #define AMDGPU_COPY_FLAGS_DATA_FORMAT_MASK             0x3f
+#define AMDGPU_COPY_FLAGS_WRITE_COMPRESS_DISABLE_SHIFT 14
+#define AMDGPU_COPY_FLAGS_WRITE_COMPRESS_DISABLE_MASK  0x1
 
 #define AMDGPU_COPY_FLAGS_SET(field, value) \
        (((__u32)(value) & AMDGPU_COPY_FLAGS_##field##_MASK) << AMDGPU_COPY_FLAGS_##field##_SHIFT)

diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c
index 9c17df2cf37b82e5ade898c859f3cb93702b4165..7e10e94624e3421d27e2ca4ccd0bd3615716da7a 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c
@@ -1741,11 +1741,12 @@ static void sdma_v7_0_emit_copy_buffer(struct amdgpu_ib *ib,
                                       uint32_t byte_count,
                                       uint32_t copy_flags)
 {
-       uint32_t num_type, data_format, max_com;
+       uint32_t num_type, data_format, max_com, write_cm;
 
        max_com = AMDGPU_COPY_FLAGS_GET(copy_flags, MAX_COMPRESSED);
        data_format = AMDGPU_COPY_FLAGS_GET(copy_flags, DATA_FORMAT);
        num_type = AMDGPU_COPY_FLAGS_GET(copy_flags, NUMBER_TYPE);
+       write_cm = AMDGPU_COPY_FLAGS_GET(copy_flags, WRITE_COMPRESS_DISABLE) ? 2 : 1;
 
        ib->ptr[ib->length_dw++] = SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_COPY) |
                SDMA_PKT_COPY_LINEAR_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR) |
@@ -1762,7 +1763,7 @@ static void sdma_v7_0_emit_copy_buffer(struct amdgpu_ib *ib,
        if ((copy_flags & (AMDGPU_COPY_FLAGS_READ_DECOMPRESSED | AMDGPU_COPY_FLAGS_WRITE_COMPRESSED)))
                ib->ptr[ib->length_dw++] = SDMA_DCC_DATA_FORMAT(data_format) | SDMA_DCC_NUM_TYPE(num_type) |
                        ((copy_flags & AMDGPU_COPY_FLAGS_READ_DECOMPRESSED) ? SDMA_DCC_READ_CM(2) : 0) |
-                       ((copy_flags & AMDGPU_COPY_FLAGS_WRITE_COMPRESSED) ? SDMA_DCC_WRITE_CM(1) : 0) |
+                       ((copy_flags & AMDGPU_COPY_FLAGS_WRITE_COMPRESSED) ? SDMA_DCC_WRITE_CM(write_cm) : 0) |
                        SDMA_DCC_MAX_COM(max_com) | SDMA_DCC_MAX_UCOM(1);
        else
                ib->ptr[ib->length_dw++] = 0;

diff --git a/include/uapi/drm/amdgpu_drm.h b/include/uapi/drm/amdgpu_drm.h
index efe5de6ce208a141499dd66d45b196f33e10886b..aaa4f3bc688b57fcdc57635ad96ec10989076299 100644 (file)
--- a/include/uapi/drm/amdgpu_drm.h
+++ b/include/uapi/drm/amdgpu_drm.h
@@ -411,13 +411,20 @@ struct drm_amdgpu_gem_userptr {
 /* GFX12 and later: */
 #define AMDGPU_TILING_GFX12_SWIZZLE_MODE_SHIFT                 0
 #define AMDGPU_TILING_GFX12_SWIZZLE_MODE_MASK                  0x7
-/* These are DCC recompression setting for memory management: */
+/* These are DCC recompression settings for memory management: */
 #define AMDGPU_TILING_GFX12_DCC_MAX_COMPRESSED_BLOCK_SHIFT     3
 #define AMDGPU_TILING_GFX12_DCC_MAX_COMPRESSED_BLOCK_MASK      0x3 /* 0:64B, 1:128B, 2:256B */
 #define AMDGPU_TILING_GFX12_DCC_NUMBER_TYPE_SHIFT              5
 #define AMDGPU_TILING_GFX12_DCC_NUMBER_TYPE_MASK               0x7 /* CB_COLOR0_INFO.NUMBER_TYPE */
 #define AMDGPU_TILING_GFX12_DCC_DATA_FORMAT_SHIFT              8
 #define AMDGPU_TILING_GFX12_DCC_DATA_FORMAT_MASK               0x3f /* [0:4]:CB_COLOR0_INFO.FORMAT, [5]:MM */
+/* When clearing the buffer or moving it from VRAM to GTT, don't compress and set DCC metadata
+ * to uncompressed. Set when parts of an allocation bypass DCC and read raw data. */
+#define AMDGPU_TILING_GFX12_DCC_WRITE_COMPRESS_DISABLE_SHIFT   14
+#define AMDGPU_TILING_GFX12_DCC_WRITE_COMPRESS_DISABLE_MASK    0x1
+/* bit gap */
+#define AMDGPU_TILING_GFX12_SCANOUT_SHIFT                      63
+#define AMDGPU_TILING_GFX12_SCANOUT_MASK                       0x1
 
 /* Set/Get helpers for tiling flags. */
 #define AMDGPU_TILING_SET(field, value) \