#define OMAP_RTC_IRQWAKEEN             0x7c
 
+#define OMAP_RTC_ALARM2_SECONDS_REG    0x80
+#define OMAP_RTC_ALARM2_MINUTES_REG    0x84
+#define OMAP_RTC_ALARM2_HOURS_REG      0x88
+#define OMAP_RTC_ALARM2_DAYS_REG       0x8c
+#define OMAP_RTC_ALARM2_MONTHS_REG     0x90
+#define OMAP_RTC_ALARM2_YEARS_REG      0x94
+
+#define OMAP_RTC_PMIC_REG              0x98
+
 /* OMAP_RTC_CTRL_REG bit fields: */
 #define OMAP_RTC_CTRL_SPLIT            BIT(7)
 #define OMAP_RTC_CTRL_DISABLE          BIT(6)
 
 /* OMAP_RTC_STATUS_REG bit fields: */
 #define OMAP_RTC_STATUS_POWER_UP       BIT(7)
+#define OMAP_RTC_STATUS_ALARM2         BIT(7)
 #define OMAP_RTC_STATUS_ALARM          BIT(6)
 #define OMAP_RTC_STATUS_1D_EVENT       BIT(5)
 #define OMAP_RTC_STATUS_1H_EVENT       BIT(4)
 #define OMAP_RTC_STATUS_BUSY           BIT(0)
 
 /* OMAP_RTC_INTERRUPTS_REG bit fields: */
+#define OMAP_RTC_INTERRUPTS_IT_ALARM2  BIT(4)
 #define OMAP_RTC_INTERRUPTS_IT_ALARM   BIT(3)
 #define OMAP_RTC_INTERRUPTS_IT_TIMER   BIT(2)
 
 /* OMAP_RTC_IRQWAKEEN bit fields: */
 #define OMAP_RTC_IRQWAKEEN_ALARM_WAKEEN        BIT(1)
 
+/* OMAP_RTC_PMIC bit fields: */
+#define OMAP_RTC_PMIC_POWER_EN_EN      BIT(16)
+
 /* OMAP_RTC_KICKER values */
 #define        KICK0_VALUE                     0x83e70b13
 #define        KICK1_VALUE                     0x95a4f1e0
        bool has_32kclk_en;
        bool has_kicker;
        bool has_irqwakeen;
+       bool has_pmic_mode;
        bool has_power_up_reset;
 };
 
        int irq_alarm;
        int irq_timer;
        u8 interrupts_reg;
+       bool is_pmic_controller;
        const struct omap_rtc_device_type *type;
 };
 
        return 0;
 }
 
+static struct omap_rtc *omap_rtc_power_off_rtc;
+
+/*
+ * omap_rtc_poweroff: RTC-controlled power off
+ *
+ * The RTC can be used to control an external PMIC via the pmic_power_en pin,
+ * which can be configured to transition to OFF on ALARM2 events.
+ *
+ * Notes:
+ * The two-second alarm offset is the shortest offset possible as the alarm
+ * registers must be set before the next timer update and the offset
+ * calculation is too heavy for everything to be done within a single access
+ * period (~15 us).
+ *
+ * Called with local interrupts disabled.
+ */
+static void omap_rtc_power_off(void)
+{
+       struct omap_rtc *rtc = omap_rtc_power_off_rtc;
+       struct rtc_time tm;
+       unsigned long now;
+       u32 val;
+
+       /* enable pmic_power_en control */
+       val = rtc_readl(rtc, OMAP_RTC_PMIC_REG);
+       rtc_writel(rtc, OMAP_RTC_PMIC_REG, val | OMAP_RTC_PMIC_POWER_EN_EN);
+
+       /* set alarm two seconds from now */
+       omap_rtc_read_time_raw(rtc, &tm);
+       bcd2tm(&tm);
+       rtc_tm_to_time(&tm, &now);
+       rtc_time_to_tm(now + 2, &tm);
+
+       if (tm2bcd(&tm) < 0) {
+               dev_err(&rtc->rtc->dev, "power off failed\n");
+               return;
+       }
+
+       rtc_wait_not_busy(rtc);
+
+       rtc_write(rtc, OMAP_RTC_ALARM2_SECONDS_REG, tm.tm_sec);
+       rtc_write(rtc, OMAP_RTC_ALARM2_MINUTES_REG, tm.tm_min);
+       rtc_write(rtc, OMAP_RTC_ALARM2_HOURS_REG, tm.tm_hour);
+       rtc_write(rtc, OMAP_RTC_ALARM2_DAYS_REG, tm.tm_mday);
+       rtc_write(rtc, OMAP_RTC_ALARM2_MONTHS_REG, tm.tm_mon);
+       rtc_write(rtc, OMAP_RTC_ALARM2_YEARS_REG, tm.tm_year);
+
+       /*
+        * enable ALARM2 interrupt
+        *
+        * NOTE: this fails on AM3352 if rtc_write (writeb) is used
+        */
+       val = rtc_read(rtc, OMAP_RTC_INTERRUPTS_REG);
+       rtc_writel(rtc, OMAP_RTC_INTERRUPTS_REG,
+                       val | OMAP_RTC_INTERRUPTS_IT_ALARM2);
+
+       /*
+        * Wait for alarm to trigger (within two seconds) and external PMIC to
+        * power off the system. Add a 500 ms margin for external latencies
+        * (e.g. debounce circuits).
+        */
+       mdelay(2500);
+}
+
 static struct rtc_class_ops omap_rtc_ops = {
        .read_time      = omap_rtc_read_time,
        .set_time       = omap_rtc_set_time,
        .has_32kclk_en  = true,
        .has_kicker     = true,
        .has_irqwakeen  = true,
+       .has_pmic_mode  = true,
 };
 
 static const struct omap_rtc_device_type omap_rtc_da830_type = {
        of_id = of_match_device(omap_rtc_of_match, &pdev->dev);
        if (of_id) {
                rtc->type = of_id->data;
+               rtc->is_pmic_controller = rtc->type->has_pmic_mode &&
+                               of_property_read_bool(pdev->dev.of_node,
+                                               "ti,system-power-controller");
        } else {
                id_entry = platform_get_device_id(pdev);
                rtc->type = (void *)id_entry->driver_data;
 
        mask = OMAP_RTC_STATUS_ALARM;
 
+       if (rtc->type->has_pmic_mode)
+               mask |= OMAP_RTC_STATUS_ALARM2;
+
        if (rtc->type->has_power_up_reset) {
                mask |= OMAP_RTC_STATUS_POWER_UP;
                if (reg & OMAP_RTC_STATUS_POWER_UP)
                        goto err;
        }
 
+       if (rtc->is_pmic_controller) {
+               if (!pm_power_off) {
+                       omap_rtc_power_off_rtc = rtc;
+                       pm_power_off = omap_rtc_power_off;
+               }
+       }
+
        return 0;
 
 err:
 {
        struct omap_rtc *rtc = platform_get_drvdata(pdev);
 
+       if (pm_power_off == omap_rtc_power_off &&
+                       omap_rtc_power_off_rtc == rtc) {
+               pm_power_off = NULL;
+               omap_rtc_power_off_rtc = NULL;
+       }
+
        device_init_wakeup(&pdev->dev, 0);
 
        /* leave rtc running, but disable irqs */