arm64: dts: apple: t8015: Add CPU caches

Add information about CPU caches in Apple A11 SoC.

Signed-off-by: Nick Chan <towinchenmi@gmail.com>
Link: https://lore.kernel.org/r/20250220-caches-v1-9-2c7011097768@gmail.com
Signed-off-by: Sven Peter <sven@svenpeter.dev>

diff --git a/arch/arm64/boot/dts/apple/t8015.dtsi b/arch/arm64/boot/dts/apple/t8015.dtsi
index 4d54afcecd50b50ed1fd386ccfc46c373e190e6b..12acf8fc8bc6bcde6b11773cadd97e9ee115f510 100644 (file)
--- a/arch/arm64/boot/dts/apple/t8015.dtsi
+++ b/arch/arm64/boot/dts/apple/t8015.dtsi
@@ -63,6 +63,9 @@
                        capacity-dmips-mhz = <633>;
                        enable-method = "spin-table";
                        device_type = "cpu";
+                       next-level-cache = <&l2_cache_0>;
+                       i-cache-size = <0x8000>;
+                       d-cache-size = <0x8000>;
                };
 
                cpu_e1: cpu@1 {
@@ -74,6 +77,9 @@
                        capacity-dmips-mhz = <633>;
                        enable-method = "spin-table";
                        device_type = "cpu";
+                       next-level-cache = <&l2_cache_0>;
+                       i-cache-size = <0x8000>;
+                       d-cache-size = <0x8000>;
                };
 
                cpu_e2: cpu@2 {
@@ -85,6 +91,9 @@
                        capacity-dmips-mhz = <633>;
                        enable-method = "spin-table";
                        device_type = "cpu";
+                       next-level-cache = <&l2_cache_0>;
+                       i-cache-size = <0x8000>;
+                       d-cache-size = <0x8000>;
                };
 
                cpu_e3: cpu@3 {
@@ -96,6 +105,9 @@
                        capacity-dmips-mhz = <633>;
                        enable-method = "spin-table";
                        device_type = "cpu";
+                       next-level-cache = <&l2_cache_0>;
+                       i-cache-size = <0x8000>;
+                       d-cache-size = <0x8000>;
                };
 
                cpu_p0: cpu@10004 {
@@ -107,6 +119,9 @@
                        capacity-dmips-mhz = <1024>;
                        enable-method = "spin-table";
                        device_type = "cpu";
+                       next-level-cache = <&l2_cache_1>;
+                       i-cache-size = <0x10000>;
+                       d-cache-size = <0x10000>;
                };
 
                cpu_p1: cpu@10005 {
@@ -118,6 +133,23 @@
                        capacity-dmips-mhz = <1024>;
                        enable-method = "spin-table";
                        device_type = "cpu";
+                       next-level-cache = <&l2_cache_1>;
+                       i-cache-size = <0x10000>;
+                       d-cache-size = <0x10000>;
+               };
+
+               l2_cache_0: l2-cache-0 {
+                       compatible = "cache";
+                       cache-level = <2>;
+                       cache-unified;
+                       cache-size = <0x100000>;
+               };
+
+               l2_cache_1: l2-cache-1 {
+                       compatible = "cache";
+                       cache-level = <2>;
+                       cache-unified;
+                       cache-size = <0x800000>;
                };
        };