ARM: dts: stm32: add USB OTG UTMI clock on stm32mp151

It's needed on STM32MP15, when using the integrated full-speed PHY. This
clock is an output of USBPHYC, and the HS USBPHYC is not attached as PHY
in this case (managed directly by dwc2 ggpio glue):

    &usbotg_hs {
    	compatible = "st,stm32mp15-fsotg", "snps,dwc2";
    	pinctrl-names = "default";
    	pinctrl-0 = <&usbotg_hs_pins_a &usbotg_fs_dp_dm_pins_a>;
    	vbus-supply = <&vbus_otg>;
    	status = "okay";
    };

USBPHYC clock output must be used, so it can be properly enabled as a
clock provider.

Without this, currently, when the dualport High-Speed USBPHYC isn't
requested by either USBH or OTG, it remains uninitialized when probing
OTG: OTG configured with full-speed PHY isn't properly clocked, resulting
in error log like:
[    2.383138] dwc2 49000000.usb-otg: dwc2_core_reset: HANG! Soft Reset
timeout GRSTCTL_CSFTRST.

Signed-off-by: Fabrice Gasnier <fabrice.gasnier@foss.st.com>
Link: https://lore.kernel.org/r/20230414084137.1050487-5-fabrice.gasnier@foss.st.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

diff --git a/arch/arm/boot/dts/stm32mp151.dtsi b/arch/arm/boot/dts/stm32mp151.dtsi
index 4e437d3f2ed66e7bcc203f3a240ad0f29d083b0b..63f4c78fcc1dc9a4cc0d76ec27ff6a8364a07280 100644 (file)
--- a/arch/arm/boot/dts/stm32mp151.dtsi
+++ b/arch/arm/boot/dts/stm32mp151.dtsi
@@ -1130,8 +1130,8 @@
                usbotg_hs: usb-otg@49000000 {
                        compatible = "st,stm32mp15-hsotg", "snps,dwc2";
                        reg = <0x49000000 0x10000>;
-                       clocks = <&rcc USBO_K>;
-                       clock-names = "otg";
+                       clocks = <&rcc USBO_K>, <&usbphyc>;
+                       clock-names = "otg", "utmi";
                        resets = <&rcc USBO_R>;
                        reset-names = "dwc2";
                        interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;