drm/xe/xe_gt_idle: use GT forcewake domain assertion

The rc6 registers used in disable_c6 function belong
to the GT forcewake domain. Hence change the forcewake
assertion to check GT forcewake domain.

v2: add fixes tag (Himal)

Fixes: 975e4a3795d4 ("drm/xe: Manually setup C6 when skip_guc_pc is set")
Signed-off-by: Riana Tauro <riana.tauro@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: Himal Prasad Ghimiray <himal.prasad.ghimiray@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240606100842.956072-2-riana.tauro@intel.com
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

diff --git a/drivers/gpu/drm/xe/xe_gt_idle.c b/drivers/gpu/drm/xe/xe_gt_idle.c
index 0109d1d2e9c40c7d02b3a7f35c54be19f2401b73..a6ab8bb4571d639dae66b7c591ef9ba5dd5cdccb 100644 (file)
--- a/drivers/gpu/drm/xe/xe_gt_idle.c
+++ b/drivers/gpu/drm/xe/xe_gt_idle.c
@@ -250,7 +250,7 @@ void xe_gt_idle_enable_c6(struct xe_gt *gt)
 void xe_gt_idle_disable_c6(struct xe_gt *gt)
 {
        xe_device_assert_mem_access(gt_to_xe(gt));
-       xe_force_wake_assert_held(gt_to_fw(gt), XE_FORCEWAKE_ALL);
+       xe_force_wake_assert_held(gt_to_fw(gt), XE_FW_GT);
 
        xe_mmio_write32(gt, RC_CONTROL, 0);
        xe_mmio_write32(gt, RC_STATE, 0);