drm/i915: Eliminate IS_MTL_DISPLAY_STEP

Stepping-specific display behavior shouldn't be tied to MTL as a
platform, but rather specifically to the Xe_LPD+ IP.  Future non-MTL
platforms may re-use this IP and will need to follow the exact same
logic and apply the same workarounds.  IS_MTL_DISPLAY_STEP() is dropped
in favor of a new macro IS_DISPLAY_IP_STEP() that only checks the
display IP version.

v2:
 - Rename macro to IS_DISPLAY_IP_STEP for consistency with the
   corresponding GT macro and handle steppings the same way.
v3:
 - Drop the automatic "STEP_" pasting.
v4:
 - Implement IS_DISPLAY_IP_STEP on top of IS_DISPLAY_IP_RANGE /
   IS_DISPLAY_STEP building blocks and make the parameters from/until
   instead of begin/fixed.  (Jani)
 - Fix usage details in comment.
v5:
 - Tweak macro comment.  (Gustavo)

Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Gustavo Sousa <gustavo.sousa@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20230821180619.650007-17-matthew.d.roper@intel.com

diff --git a/drivers/gpu/drm/i915/display/intel_display_device.h b/drivers/gpu/drm/i915/display/intel_display_device.h
index eb630a946343fd0e912f355f2434ea6cbfdd3f02..8198401aa5be8074202595803506a9f03f9fd5c2 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_display_device.h
+++ b/drivers/gpu/drm/i915/display/intel_display_device.h
@@ -72,6 +72,31 @@ struct drm_printer;
 #define OVERLAY_NEEDS_PHYSICAL(i915)   (DISPLAY_INFO(i915)->overlay_needs_physical)
 #define SUPPORTS_TV(i915)              (DISPLAY_INFO(i915)->supports_tv)
 
+/* Check that device has a display IP version within the specific range. */
+#define IS_DISPLAY_IP_RANGE(__i915, from, until) ( \
+       BUILD_BUG_ON_ZERO((from) < IP_VER(2, 0)) + \
+       (DISPLAY_VER_FULL(__i915) >= (from) && \
+        DISPLAY_VER_FULL(__i915) <= (until)))
+
+/*
+ * Check if a device has a specific IP version as well as a stepping within the
+ * specified range [from, until).  The lower bound is inclusive, the upper
+ * bound is exclusive.  The most common use-case of this macro is for checking
+ * bounds for workarounds, which usually have a stepping ("from") at which the
+ * hardware issue is first present and another stepping ("until") at which a
+ * hardware fix is present and the software workaround is no longer necessary.
+ * E.g.,
+ *
+ *    IS_DISPLAY_IP_STEP(i915, IP_VER(14, 0), STEP_A0, STEP_B2)
+ *    IS_DISPLAY_IP_STEP(i915, IP_VER(14, 0), STEP_C0, STEP_FOREVER)
+ *
+ * "STEP_FOREVER" can be passed as "until" for workarounds that have no upper
+ * stepping bound for the specified IP version.
+ */
+#define IS_DISPLAY_IP_STEP(__i915, ipver, from, until) \
+       (IS_DISPLAY_IP_RANGE((__i915), (ipver), (ipver)) && \
+        IS_DISPLAY_STEP((__i915), (from), (until)))
+
 struct intel_display_runtime_info {
        struct {
                u16 ver;

diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c
index 25382022cd2768301c417a37e456526deed7547b..1c6d467cec267c0339d7390b2470b54d152c1562 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_fbc.c
+++ b/drivers/gpu/drm/i915/display/intel_fbc.c
@@ -50,6 +50,7 @@
 #include "i915_vma.h"
 #include "intel_cdclk.h"
 #include "intel_de.h"
+#include "intel_display_device.h"
 #include "intel_display_trace.h"
 #include "intel_display_types.h"
 #include "intel_fbc.h"
@@ -1100,7 +1101,7 @@ static int intel_fbc_check_plane(struct intel_atomic_state *state,
 
        /* Wa_14016291713 */
        if ((IS_DISPLAY_VER(i915, 12, 13) ||
-            IS_MTL_DISPLAY_STEP(i915, STEP_A0, STEP_C0)) &&
+            IS_DISPLAY_IP_STEP(i915, IP_VER(14, 0), STEP_A0, STEP_C0)) &&
            crtc_state->has_psr) {
                plane_state->no_fbc_reason = "PSR1 enabled (Wa_14016291713)";
                return 0;

diff --git a/drivers/gpu/drm/i915/display/intel_pmdemand.c b/drivers/gpu/drm/i915/display/intel_pmdemand.c
index f7608d36363469bcbe2ee41268f6386ce6ee2924..744e332fa2afa3f9d31b92752d2b8c2cb9d35b3b 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_pmdemand.c
+++ b/drivers/gpu/drm/i915/display/intel_pmdemand.c
@@ -92,7 +92,7 @@ int intel_pmdemand_init(struct drm_i915_private *i915)
                                     &pmdemand_state->base,
                                     &intel_pmdemand_funcs);
 
-       if (IS_MTL_DISPLAY_STEP(i915, STEP_A0, STEP_C0))
+       if (IS_DISPLAY_IP_STEP(i915, IP_VER(14, 0), STEP_A0, STEP_C0))
                /* Wa_14016740474 */
                intel_de_rmw(i915, XELPD_CHICKEN_DCPR_3, 0, DMD_RSP_TIMEOUT_DISABLE);
 

diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index 97d5eef10130df56bbeccb292363800e849d664f..72887c29fb515dff805c57edda5cb06e2bfd3bc7 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -1360,7 +1360,7 @@ static void wm_optimization_wa(struct intel_dp *intel_dp,
        bool set_wa_bit = false;
 
        /* Wa_14015648006 */
-       if (IS_MTL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0) ||
+       if (IS_DISPLAY_IP_STEP(dev_priv, IP_VER(14, 0), STEP_A0, STEP_B0) ||
            IS_DISPLAY_VER(dev_priv, 11, 13))
                set_wa_bit |= crtc_state->wm_level_disabled;
 
@@ -1447,7 +1447,7 @@ static void intel_psr_enable_source(struct intel_dp *intel_dp,
                 * All supported adlp panels have 1-based X granularity, this may
                 * cause issues if non-supported panels are used.
                 */
-               if (IS_MTL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
+               if (IS_DISPLAY_IP_STEP(dev_priv, IP_VER(14, 0), STEP_A0, STEP_B0))
                        intel_de_rmw(dev_priv, MTL_CHICKEN_TRANS(cpu_transcoder), 0,
                                     ADLP_1_BASED_X_GRANULARITY);
                else if (IS_ALDERLAKE_P(dev_priv))
@@ -1455,7 +1455,7 @@ static void intel_psr_enable_source(struct intel_dp *intel_dp,
                                     ADLP_1_BASED_X_GRANULARITY);
 
                /* Wa_16012604467:adlp,mtl[a0,b0] */
-               if (IS_MTL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
+               if (IS_DISPLAY_IP_STEP(dev_priv, IP_VER(14, 0), STEP_A0, STEP_B0))
                        intel_de_rmw(dev_priv,
                                     MTL_CLKGATE_DIS_TRANS(cpu_transcoder), 0,
                                     MTL_CLKGATE_DIS_TRANS_DMASC_GATING_DIS);
@@ -1613,7 +1613,7 @@ static void intel_psr_disable_locked(struct intel_dp *intel_dp)
 
        if (intel_dp->psr.psr2_enabled) {
                /* Wa_16012604467:adlp,mtl[a0,b0] */
-               if (IS_MTL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
+               if (IS_DISPLAY_IP_STEP(dev_priv, IP_VER(14, 0), STEP_A0, STEP_B0))
                        intel_de_rmw(dev_priv,
                                     MTL_CLKGATE_DIS_TRANS(cpu_transcoder),
                                     MTL_CLKGATE_DIS_TRANS_DMASC_GATING_DIS, 0);
@@ -2087,7 +2087,7 @@ int intel_psr2_sel_fetch_update(struct intel_atomic_state *state,
                goto skip_sel_fetch_set_loop;
 
        /* Wa_14014971492 */
-       if ((IS_MTL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0) ||
+       if ((IS_DISPLAY_IP_STEP(dev_priv, IP_VER(14, 0), STEP_A0, STEP_B0) ||
             IS_ALDERLAKE_P(dev_priv) || IS_TIGERLAKE(dev_priv)) &&
            crtc_state->splitter.enable)
                pipe_clip.y1 = 0;

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index fb4813fc084f51ad0a58cb86986bccb5741a0514..3d802701490fced4e76cfaf17d7a4199d2aa43f3 100644 (file)
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -437,6 +437,8 @@ static inline struct intel_gt *to_gt(struct drm_i915_private *i915)
        (MEDIA_VER(i915) >= (from) && MEDIA_VER(i915) <= (until))
 
 #define DISPLAY_VER(i915)      (DISPLAY_RUNTIME_INFO(i915)->ip.ver)
+#define DISPLAY_VER_FULL(i915) IP_VER(DISPLAY_RUNTIME_INFO(i915)->ip.ver, \
+                                      DISPLAY_RUNTIME_INFO(i915)->ip.rel)
 #define IS_DISPLAY_VER(i915, from, until) \
        (DISPLAY_VER(i915) >= (from) && DISPLAY_VER(i915) <= (until))
 
@@ -662,10 +664,6 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
        (IS_SUBPLATFORM(__i915, INTEL_METEORLAKE, INTEL_SUBPLATFORM_##variant) && \
         IS_GRAPHICS_STEP(__i915, since, until))
 
-#define IS_MTL_DISPLAY_STEP(__i915, since, until) \
-       (IS_METEORLAKE(__i915) && \
-        IS_DISPLAY_STEP(__i915, since, until))
-
 #define IS_MTL_MEDIA_STEP(__i915, since, until) \
        (IS_METEORLAKE(__i915) && \
         IS_MEDIA_STEP(__i915, since, until))