ARM: dts: rockchip: Add i2s0 node for RV1126

Add i2s0 node and possible pinctrl for Rockchip RV1126

Signed-off-by: Karthikeyan Krishnasamy <karthikeyan@linumiz.com>
Link: https://lore.kernel.org/r/20240903105245.715899-3-karthikeyan@linumiz.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>

diff --git a/arch/arm/boot/dts/rockchip/rv1126-pinctrl.dtsi b/arch/arm/boot/dts/rockchip/rv1126-pinctrl.dtsi
index be666b25b830297c2e0eeae4f2f6131562c8c9eb..c6706fa8bf133a046b2c8dc249fab9801c092aaf 100644 (file)
--- a/arch/arm/boot/dts/rockchip/rv1126-pinctrl.dtsi
+++ b/arch/arm/boot/dts/rockchip/rv1126-pinctrl.dtsi
@@ -123,6 +123,108 @@
                                <1 RK_PD7 3 &pcfg_pull_none>;
                };
        };
+       i2s0 {
+               i2s0m0_lrck_tx: i2s0m0-lrck-tx {
+                       rockchip,pins =
+                       /* i2s0_lrck_tx_m0 */
+                       <3 RK_PD3 1 &pcfg_pull_none>;
+               };
+               i2s0m0_lrck_rx: i2s0m0-lrck-rx {
+                       rockchip,pins =
+                       /* i2s0_lrck_rx_m0 */
+                       <3 RK_PD4 1 &pcfg_pull_none>;
+               };
+               i2s0m0_mclk: i2s0m0-mclk {
+                       rockchip,pins =
+                       /* i2s0_mclk_m0 */
+                       <3 RK_PD2 1 &pcfg_pull_none>;
+               };
+               i2s0m0_sclk_rx: i2s0m0-sclk-rx {
+                       rockchip,pins =
+                       /* i2s0_sclk_rx_m0 */
+                       <3 RK_PD1 1 &pcfg_pull_none>;
+               };
+               i2s0m0_sclk_tx: i2s0m0-sclk-tx {
+                       rockchip,pins =
+                       /* i2s0_sclk_tx_m0 */
+                       <3 RK_PD0 1 &pcfg_pull_none>;
+               };
+               i2s0m0_sdi0: i2s0m0-sdi0 {
+                       rockchip,pins =
+                       /* i2s0_sdi0_m0 */
+                       <3 RK_PD6 1 &pcfg_pull_none>;
+               };
+               i2s0m0_sdo0: i2s0m0-sdo0 {
+                       rockchip,pins =
+                       /* i2s0_sdo0_m0 */
+                       <3 RK_PD5 1 &pcfg_pull_none>;
+               };
+               i2s0m0_sdo1_sdi3: i2s0m0-sdo1-sdi3 {
+                       rockchip,pins =
+                       /* i2s0_sdo1_sdi3_m0 */
+                       <3 RK_PD7 1 &pcfg_pull_none>;
+               };
+               i2s0m0_sdo2_sdi2: i2s0m0-sdo2-sdi2 {
+                       rockchip,pins =
+                       /* i2s0_sdo2_sdi2_m0 */
+                       <4 RK_PA0 1 &pcfg_pull_none>;
+               };
+               i2s0m0_sdo3_sdi1: i2s0m0-sdo3-sdi1 {
+                       rockchip,pins =
+                       /* i2s0_sdo3_sdi1_m0 */
+                       <4 RK_PA1 1 &pcfg_pull_none>;
+               };
+               i2s0m1_lrck_tx: i2s0m1-lrck-tx {
+                       rockchip,pins =
+                       /* i2s0_lrck_tx_m1 */
+                       <3 RK_PA5 3 &pcfg_pull_none>;
+               };
+               i2s0m1_lrck_rx: i2s0m1-lrck-rx {
+                       rockchip,pins =
+                       /* i2s0_lrck_rx_m1 */
+                       <3 RK_PB2 3 &pcfg_pull_none>;
+               };
+               i2s0m1_mclk: i2s0m1-mclk {
+                       rockchip,pins =
+                       /* i2s0_mclk_m1 */
+                       <3 RK_PB0 3 &pcfg_pull_none>;
+               };
+               i2s0m1_sclk_rx: i2s0m1-sclk-rx {
+                       rockchip,pins =
+                       /* i2s0_sclk_rx_m1 */
+                       <3 RK_PB1 3 &pcfg_pull_none>;
+               };
+               i2s0m1_sclk_tx: i2s0m1-sclk-tx {
+                       rockchip,pins =
+                       /* i2s0_sclk_tx_m1 */
+                       <3 RK_PA4 3 &pcfg_pull_none>;
+               };
+               i2s0m1_sdi0: i2s0m1-sdi0 {
+                       rockchip,pins =
+                       /* i2s0_sdi0_m1 */
+                       <3 RK_PA7 3 &pcfg_pull_none>;
+               };
+               i2s0m1_sdo0: i2s0m1-sdo0 {
+                       rockchip,pins =
+                       /* i2s0_sdo0_m1 */
+                       <3 RK_PA6 3 &pcfg_pull_none>;
+               };
+               i2s0m1_sdo1_sdi3: i2s0m1-sdo1-sdi3 {
+                       rockchip,pins =
+                       /* i2s0_sdo1_sdi3_m1 */
+                       <3 RK_PB3 3 &pcfg_pull_none>;
+               };
+               i2s0m1_sdo2_sdi2: i2s0m1-sdo2-sdi2 {
+                       rockchip,pins =
+                       /* i2s0_sdo2_sdi2_m1 */
+                       <3 RK_PB4 3 &pcfg_pull_none>;
+               };
+               i2s0m1_sdo3_sdi1: i2s0m1-sdo3-sdi1 {
+                       rockchip,pins =
+                       /* i2s0_sdo3_sdi1_m1 */
+                       <3 RK_PB5 3 &pcfg_pull_none>;
+               };
+       };
        pwm2 {
                /omit-if-no-ref/
                pwm2m0_pins: pwm2m0-pins {

diff --git a/arch/arm/boot/dts/rockchip/rv1126.dtsi b/arch/arm/boot/dts/rockchip/rv1126.dtsi
index cf7575e76a691c3b8fbcdfc0488d96b4b63c205b..f3d278bb4d8f4ee4191b3136caff3b3c69e110cc 100644 (file)
--- a/arch/arm/boot/dts/rockchip/rv1126.dtsi
+++ b/arch/arm/boot/dts/rockchip/rv1126.dtsi
@@ -434,6 +434,32 @@
                clock-names = "pclk", "timer";
        };
 
+       i2s0: i2s@ff800000 {
+               compatible = "rockchip,rv1126-i2s-tdm";
+               reg = <0xff800000 0x1000>;
+               interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
+               clocks = <&cru MCLK_I2S0_TX>, <&cru MCLK_I2S0_RX>, <&cru HCLK_I2S0>;
+               clock-names = "mclk_tx", "mclk_rx", "hclk";
+               dmas = <&dmac 20>, <&dmac 19>;
+               dma-names = "tx", "rx";
+               pinctrl-names = "default";
+               pinctrl-0 = <&i2s0m0_sclk_tx>,
+                            <&i2s0m0_sclk_rx>,
+                            <&i2s0m0_mclk>,
+                            <&i2s0m0_lrck_tx>,
+                            <&i2s0m0_lrck_rx>,
+                            <&i2s0m0_sdi0>,
+                            <&i2s0m0_sdo0>,
+                            <&i2s0m0_sdo1_sdi3>,
+                            <&i2s0m0_sdo2_sdi2>,
+                            <&i2s0m0_sdo3_sdi1>;
+               resets = <&cru SRST_I2S0_TX_M>, <&cru SRST_I2S0_RX_M>;
+               reset-names = "tx-m", "rx-m";
+               rockchip,grf = <&grf>;
+               #sound-dai-cells = <0>;
+               status = "disabled";
+       };
+
        vop: vop@ffb00000 {
                compatible = "rockchip,rv1126-vop";
                reg = <0xffb00000 0x200>, <0xffb00a00 0x400>;