dsb(st);
 }
 
-#ifdef CONFIG_CACHE_PL310
-static inline void cache_wait(void __iomem *reg, unsigned long mask)
-{
-       /* cache operations by line are atomic on PL310 */
-}
-#else
-#define cache_wait     l2c_wait_mask
-#endif
-
-static inline void cache_sync(void)
-{
-       void __iomem *base = l2x0_base;
-
-       writel_relaxed(0, base + sync_reg_offset);
-       cache_wait(base + L2X0_CACHE_SYNC, 1);
-}
-
-#if defined(CONFIG_PL310_ERRATA_588369) || defined(CONFIG_PL310_ERRATA_727915)
-static inline void debug_writel(unsigned long val)
-{
-       l2c_set_debug(l2x0_base, val);
-}
-#else
-/* Optimised out for non-errata case */
-static inline void debug_writel(unsigned long val)
-{
-}
-#endif
-
-static void l2x0_cache_sync(void)
-{
-       unsigned long flags;
-
-       raw_spin_lock_irqsave(&l2x0_lock, flags);
-       cache_sync();
-       raw_spin_unlock_irqrestore(&l2x0_lock, flags);
-}
-
-static void __l2x0_flush_all(void)
-{
-       debug_writel(0x03);
-       __l2c_op_way(l2x0_base + L2X0_CLEAN_INV_WAY);
-       cache_sync();
-       debug_writel(0x00);
-}
-
-static void l2x0_flush_all(void)
-{
-       unsigned long flags;
-
-       /* clean all ways */
-       raw_spin_lock_irqsave(&l2x0_lock, flags);
-       __l2x0_flush_all();
-       raw_spin_unlock_irqrestore(&l2x0_lock, flags);
-}
-
-static void l2x0_disable(void)
-{
-       unsigned long flags;
-
-       raw_spin_lock_irqsave(&l2x0_lock, flags);
-       __l2x0_flush_all();
-       l2c_write_sec(0, l2x0_base, L2X0_CTRL);
-       dsb(st);
-       raw_spin_unlock_irqrestore(&l2x0_lock, flags);
-}
-
 static void l2c_save(void __iomem *base)
 {
        l2x0_saved_regs.aux_ctrl = readl_relaxed(l2x0_base + L2X0_AUX_CTRL);
 static void aurora_pa_range(unsigned long start, unsigned long end,
                        unsigned long offset)
 {
+       void __iomem *base = l2x0_base;
        unsigned long flags;
 
        raw_spin_lock_irqsave(&l2x0_lock, flags);
-       writel_relaxed(start, l2x0_base + AURORA_RANGE_BASE_ADDR_REG);
-       writel_relaxed(end, l2x0_base + offset);
+       writel_relaxed(start, base + AURORA_RANGE_BASE_ADDR_REG);
+       writel_relaxed(end, base + offset);
        raw_spin_unlock_irqrestore(&l2x0_lock, flags);
 
-       cache_sync();
+       writel_relaxed(0, base + AURORA_SYNC_REG);
 }
 
 static void aurora_inv_range(unsigned long start, unsigned long end)
        }
 }
 
+static void aurora_flush_all(void)
+{
+       void __iomem *base = l2x0_base;
+       unsigned long flags;
+
+       /* clean all ways */
+       raw_spin_lock_irqsave(&l2x0_lock, flags);
+       __l2c_op_way(base + L2X0_CLEAN_INV_WAY);
+       raw_spin_unlock_irqrestore(&l2x0_lock, flags);
+
+       writel_relaxed(0, base + AURORA_SYNC_REG);
+}
+
+static void aurora_cache_sync(void)
+{
+       writel_relaxed(0, l2x0_base + AURORA_SYNC_REG);
+}
+
+static void aurora_disable(void)
+{
+       void __iomem *base = l2x0_base;
+       unsigned long flags;
+
+       raw_spin_lock_irqsave(&l2x0_lock, flags);
+       __l2c_op_way(base + L2X0_CLEAN_INV_WAY);
+       writel_relaxed(0, base + AURORA_SYNC_REG);
+       l2c_write_sec(0, base, L2X0_CTRL);
+       dsb(st);
+       raw_spin_unlock_irqrestore(&l2x0_lock, flags);
+}
+
 static void aurora_save(void __iomem *base)
 {
        l2x0_saved_regs.ctrl = readl_relaxed(base + L2X0_CTRL);
                .inv_range   = aurora_inv_range,
                .clean_range = aurora_clean_range,
                .flush_range = aurora_flush_range,
-               .flush_all   = l2x0_flush_all,
-               .disable     = l2x0_disable,
-               .sync        = l2x0_cache_sync,
+               .flush_all   = aurora_flush_all,
+               .disable     = aurora_disable,
+               .sync        = aurora_cache_sync,
                .resume      = l2c_resume,
        },
 };