u64                     association_id;
 
-       u64                     cap;
-
        struct list_head        ctrl_list;      /* rport->ctrl_list */
 
        struct blk_mq_tag_set   admin_tag_set;
         * prior connection values
         */
 
-       ret = nvmf_reg_read64(&ctrl->ctrl, NVME_REG_CAP, &ctrl->cap);
+       ret = nvmf_reg_read64(&ctrl->ctrl, NVME_REG_CAP, &ctrl->ctrl.cap);
        if (ret) {
                dev_err(ctrl->ctrl.device,
                        "prop_get NVME_REG_CAP failed\n");
        }
 
        ctrl->ctrl.sqsize =
-               min_t(int, NVME_CAP_MQES(ctrl->cap) + 1, ctrl->ctrl.sqsize);
+               min_t(int, NVME_CAP_MQES(ctrl->ctrl.cap) + 1, ctrl->ctrl.sqsize);
 
-       ret = nvme_enable_ctrl(&ctrl->ctrl, ctrl->cap);
+       ret = nvme_enable_ctrl(&ctrl->ctrl, ctrl->ctrl.cap);
        if (ret)
                goto out_disconnect_admin_queue;
 
 
        u32 ctrl_config;
        u32 queue_count;
 
+       u64 cap;
        u32 page_size;
        u32 max_hw_sectors;
        u16 oncs;
 
        if (shutdown)
                nvme_shutdown_ctrl(&dev->ctrl);
        else
-               nvme_disable_ctrl(&dev->ctrl, lo_hi_readq(
-                                               dev->bar + NVME_REG_CAP));
+               nvme_disable_ctrl(&dev->ctrl, dev->ctrl.cap);
 
        spin_lock_irq(&nvmeq->q_lock);
        nvme_process_cq(nvmeq);
 {
        int result;
        u32 aqa;
-       u64 cap = lo_hi_readq(dev->bar + NVME_REG_CAP);
        struct nvme_queue *nvmeq;
 
        result = nvme_remap_bar(dev, db_bar_size(dev, 0));
                return result;
 
        dev->subsystem = readl(dev->bar + NVME_REG_VS) >= NVME_VS(1, 1, 0) ?
-                                               NVME_CAP_NSSRC(cap) : 0;
+                               NVME_CAP_NSSRC(dev->ctrl.cap) : 0;
 
        if (dev->subsystem &&
            (readl(dev->bar + NVME_REG_CSTS) & NVME_CSTS_NSSRO))
                writel(NVME_CSTS_NSSRO, dev->bar + NVME_REG_CSTS);
 
-       result = nvme_disable_ctrl(&dev->ctrl, cap);
+       result = nvme_disable_ctrl(&dev->ctrl, dev->ctrl.cap);
        if (result < 0)
                return result;
 
        lo_hi_writeq(nvmeq->sq_dma_addr, dev->bar + NVME_REG_ASQ);
        lo_hi_writeq(nvmeq->cq_dma_addr, dev->bar + NVME_REG_ACQ);
 
-       result = nvme_enable_ctrl(&dev->ctrl, cap);
+       result = nvme_enable_ctrl(&dev->ctrl, dev->ctrl.cap);
        if (result)
                return result;
 
 
 static int nvme_pci_enable(struct nvme_dev *dev)
 {
-       u64 cap;
        int result = -ENOMEM;
        struct pci_dev *pdev = to_pci_dev(dev->dev);
 
        if (result < 0)
                return result;
 
-       cap = lo_hi_readq(dev->bar + NVME_REG_CAP);
+       dev->ctrl.cap = lo_hi_readq(dev->bar + NVME_REG_CAP);
 
-       dev->q_depth = min_t(int, NVME_CAP_MQES(cap) + 1, NVME_Q_DEPTH);
-       dev->db_stride = 1 << NVME_CAP_STRIDE(cap);
+       dev->q_depth = min_t(int, NVME_CAP_MQES(dev->ctrl.cap) + 1,
+                               NVME_Q_DEPTH);
+       dev->db_stride = 1 << NVME_CAP_STRIDE(dev->ctrl.cap);
        dev->dbs = dev->bar + 4096;
 
        /*
                        dev->q_depth);
        } else if (pdev->vendor == PCI_VENDOR_ID_SAMSUNG &&
                   (pdev->device == 0xa821 || pdev->device == 0xa822) &&
-                  NVME_CAP_MQES(cap) == 0) {
+                  NVME_CAP_MQES(dev->ctrl.cap) == 0) {
                dev->q_depth = 64;
                dev_err(dev->ctrl.device, "detected PM1725 NVMe controller, "
                         "set queue depth=%u\n", dev->q_depth);
 
        struct blk_mq_tag_set   admin_tag_set;
        struct nvme_rdma_device *device;
 
-       u64                     cap;
        u32                     max_fr_pages;
 
        struct sockaddr_storage addr;
 
        set_bit(NVME_RDMA_Q_LIVE, &ctrl->queues[0].flags);
 
-       ret = nvme_enable_ctrl(&ctrl->ctrl, ctrl->cap);
+       ret = nvme_enable_ctrl(&ctrl->ctrl, ctrl->ctrl.cap);
        if (ret)
                goto requeue;
 
 
        set_bit(NVME_RDMA_Q_LIVE, &ctrl->queues[0].flags);
 
-       error = nvmf_reg_read64(&ctrl->ctrl, NVME_REG_CAP, &ctrl->cap);
+       error = nvmf_reg_read64(&ctrl->ctrl, NVME_REG_CAP,
+                       &ctrl->ctrl.cap);
        if (error) {
                dev_err(ctrl->ctrl.device,
                        "prop_get NVME_REG_CAP failed\n");
        }
 
        ctrl->ctrl.sqsize =
-               min_t(int, NVME_CAP_MQES(ctrl->cap), ctrl->ctrl.sqsize);
+               min_t(int, NVME_CAP_MQES(ctrl->ctrl.cap), ctrl->ctrl.sqsize);
 
-       error = nvme_enable_ctrl(&ctrl->ctrl, ctrl->cap);
+       error = nvme_enable_ctrl(&ctrl->ctrl, ctrl->ctrl.cap);
        if (error)
                goto out_cleanup_queue;
 
 
        struct blk_mq_tag_set   admin_tag_set;
 
        struct list_head        list;
-       u64                     cap;
        struct blk_mq_tag_set   tag_set;
        struct nvme_loop_iod    async_event_iod;
        struct nvme_ctrl        ctrl;
        if (error)
                goto out_cleanup_queue;
 
-       error = nvmf_reg_read64(&ctrl->ctrl, NVME_REG_CAP, &ctrl->cap);
+       error = nvmf_reg_read64(&ctrl->ctrl, NVME_REG_CAP, &ctrl->ctrl.cap);
        if (error) {
                dev_err(ctrl->ctrl.device,
                        "prop_get NVME_REG_CAP failed\n");
        }
 
        ctrl->ctrl.sqsize =
-               min_t(int, NVME_CAP_MQES(ctrl->cap), ctrl->ctrl.sqsize);
+               min_t(int, NVME_CAP_MQES(ctrl->ctrl.cap), ctrl->ctrl.sqsize);
 
-       error = nvme_enable_ctrl(&ctrl->ctrl, ctrl->cap);
+       error = nvme_enable_ctrl(&ctrl->ctrl, ctrl->ctrl.cap);
        if (error)
                goto out_cleanup_queue;