drm/amd/display: Move the memory allocation out of dcn20_validate_bandwidth_fp().

dcn20_validate_bandwidth_fp() is invoked while FPU access has been
enabled. FPU access requires disabling preemption even on PREEMPT_RT.
It is not possible to allocate memory with disabled preemption even with
GFP_ATOMIC on PREEMPT_RT.

Move the memory allocation before FPU access is enabled.
To preserve previous "clean" state of "pipes" add a memset() before the
second invocation of dcn20_validate_bandwidth_internal() where the
variable is used.

Acked-by: Harry Wentland <harry.wentland@amd.com>
Reviewed-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de>
Signed-off-by: Hamza Mahfooz <hamza.mahfooz@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
index 2820393d5c6f1cb5afc3793a4f9623d960e92e6c..768fef798cf1c05f0bab48173d07c4d08fdd3623 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
@@ -2141,9 +2141,17 @@ bool dcn20_validate_bandwidth(struct dc *dc, struct dc_state *context,
                bool fast_validate)
 {
        bool voltage_supported;
+       display_e2e_pipe_params_st *pipes;
+
+       pipes = kcalloc(dc->res_pool->pipe_count, sizeof(display_e2e_pipe_params_st), GFP_KERNEL);
+       if (!pipes)
+               return false;
+
        DC_FP_START();
-       voltage_supported = dcn20_validate_bandwidth_fp(dc, context, fast_validate);
+       voltage_supported = dcn20_validate_bandwidth_fp(dc, context, fast_validate, pipes);
        DC_FP_END();
+
+       kfree(pipes);
        return voltage_supported;
 }
 

diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c b/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c
index e77a88db777a46cc21d9791d2fbf5a89c66d7d32..7fc8b18096ba87c835d720d72d18175d10aaeaac 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c
@@ -1925,7 +1925,7 @@ void dcn20_patch_bounding_box(struct dc *dc, struct _vcs_dpi_soc_bounding_box_st
 }
 
 static bool dcn20_validate_bandwidth_internal(struct dc *dc, struct dc_state *context,
-               bool fast_validate)
+               bool fast_validate, display_e2e_pipe_params_st *pipes)
 {
        bool out = false;
 
@@ -1934,7 +1934,6 @@ static bool dcn20_validate_bandwidth_internal(struct dc *dc, struct dc_state *co
        int vlevel = 0;
        int pipe_split_from[MAX_PIPES];
        int pipe_cnt = 0;
-       display_e2e_pipe_params_st *pipes = kzalloc(dc->res_pool->pipe_count * sizeof(display_e2e_pipe_params_st), GFP_ATOMIC);
        DC_LOGGER_INIT(dc->ctx->logger);
 
        BW_VAL_TRACE_COUNT();
@@ -1969,16 +1968,14 @@ validate_fail:
        out = false;
 
 validate_out:
-       kfree(pipes);
 
        BW_VAL_TRACE_FINISH();
 
        return out;
 }
 
-bool dcn20_validate_bandwidth_fp(struct dc *dc,
-                                struct dc_state *context,
-                                bool fast_validate)
+bool dcn20_validate_bandwidth_fp(struct dc *dc, struct dc_state *context,
+                                bool fast_validate, display_e2e_pipe_params_st *pipes)
 {
        bool voltage_supported = false;
        bool full_pstate_supported = false;
@@ -1997,11 +1994,11 @@ bool dcn20_validate_bandwidth_fp(struct dc *dc,
        ASSERT(context != dc->current_state);
 
        if (fast_validate) {
-               return dcn20_validate_bandwidth_internal(dc, context, true);
+               return dcn20_validate_bandwidth_internal(dc, context, true, pipes);
        }
 
        // Best case, we support full UCLK switch latency
-       voltage_supported = dcn20_validate_bandwidth_internal(dc, context, false);
+       voltage_supported = dcn20_validate_bandwidth_internal(dc, context, false, pipes);
        full_pstate_supported = context->bw_ctx.bw.dcn.clk.p_state_change_support;
 
        if (context->bw_ctx.dml.soc.dummy_pstate_latency_us == 0 ||
@@ -2013,7 +2010,8 @@ bool dcn20_validate_bandwidth_fp(struct dc *dc,
        // Fallback: Try to only support G6 temperature read latency
        context->bw_ctx.dml.soc.dram_clock_change_latency_us = context->bw_ctx.dml.soc.dummy_pstate_latency_us;
 
-       voltage_supported = dcn20_validate_bandwidth_internal(dc, context, false);
+       memset(pipes, 0, dc->res_pool->pipe_count * sizeof(display_e2e_pipe_params_st));
+       voltage_supported = dcn20_validate_bandwidth_internal(dc, context, false, pipes);
        dummy_pstate_supported = context->bw_ctx.bw.dcn.clk.p_state_change_support;
 
        if (voltage_supported && (dummy_pstate_supported || !(context->stream_count))) {

diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.h b/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.h
index a81a0b9e688420861424a87a9b4124fcb0d79b45..b6c34198ddc8615cd88ef31c0158dc9c78ac6571 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.h
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.h
@@ -61,9 +61,8 @@ void dcn20_update_bounding_box(struct dc *dc,
                               unsigned int num_states);
 void dcn20_patch_bounding_box(struct dc *dc,
                              struct _vcs_dpi_soc_bounding_box_st *bb);
-bool dcn20_validate_bandwidth_fp(struct dc *dc,
-                                struct dc_state *context,
-                                bool fast_validate);
+bool dcn20_validate_bandwidth_fp(struct dc *dc, struct dc_state *context,
+                                bool fast_validate, display_e2e_pipe_params_st *pipes);
 void dcn20_fpu_set_wm_ranges(int i,
                             struct pp_smu_wm_range_sets *ranges,
                             struct _vcs_dpi_soc_bounding_box_st *loaded_bb);