{
        u32 cfg, tmp;
        struct fimc_vid_cap *vid_cap = &fimc->vid_cap;
+       u32 csis_data_alignment = 32;
 
        cfg = readl(fimc->regs + S5P_CIGCTRL);
 
                                 vid_cap->mf.code);
                        return -EINVAL;
                }
-               tmp |= (cam->csi_data_align == 32) << 8;
+               tmp |= (csis_data_alignment == 32) << 8;
 
                writel(tmp, fimc->regs + S5P_CSIIMGFMT);
 
 
  *                       multiple of 2^pix_width_alignment
  * @code: corresponding media bus code
  * @fmt_reg: S5PCSIS_CONFIG register value
+ * @data_alignment: MIPI-CSI data alignment in bits
  */
 struct csis_pix_format {
        unsigned int pix_width_alignment;
        enum v4l2_mbus_pixelcode code;
        u32 fmt_reg;
+       u8 data_alignment;
 };
 
 static const struct csis_pix_format s5pcsis_formats[] = {
        {
                .code = V4L2_MBUS_FMT_VYUY8_2X8,
                .fmt_reg = S5PCSIS_CFG_FMT_YCBCR422_8BIT,
+               .data_alignment = 32,
        }, {
                .code = V4L2_MBUS_FMT_JPEG_1X8,
                .fmt_reg = S5PCSIS_CFG_FMT_USER(1),
+               .data_alignment = 32,
        },
 };
 
        s5pcsis_set_hsync_settle(state, pdata->hs_settle);
 
        val = s5pcsis_read(state, S5PCSIS_CTRL);
-       if (pdata->alignment == 32)
+       if (state->csis_fmt->data_alignment == 32)
                val |= S5PCSIS_CTRL_ALIGN_32BIT;
        else /* 24-bits */
                val &= ~S5PCSIS_CTRL_ALIGN_32BIT;