Explicitly set the VA width to 48 bits for the x86_64-only PXXV48_4K VM
mode instead of asserting the guest VA width is 48 bits.  The fact that
KVM supports 5-level paging is irrelevant unless the selftests opt-in to
5-level paging by setting CR4.LA57 for the guest.  The overzealous
assert prevents running the selftests on a kernel with 5-level paging
enabled.
Incorporate LA57 into the assert instead of removing the assert entirely
as a sanity check of KVM's CPUID output.
Fixes: 567a9f1e9deb ("KVM: selftests: Introduce VM_MODE_PXXV48_4K")
Reported-by: Sergio Perez Gonzalez <sergio.perez.gonzalez@intel.com>
Cc: Adriana Cervantes Jimenez <adriana.cervantes.jimenez@intel.com>
Cc: Peter Xu <peterx@redhat.com>
Signed-off-by: Sean Christopherson <sean.j.christopherson@intel.com>
Message-Id: <
20200528021530.28091-1-sean.j.christopherson@intel.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
 
        case VM_MODE_PXXV48_4K:
 #ifdef __x86_64__
                kvm_get_cpu_address_width(&vm->pa_bits, &vm->va_bits);
-               TEST_ASSERT(vm->va_bits == 48, "Linear address width "
-                           "(%d bits) not supported", vm->va_bits);
+               /*
+                * Ignore KVM support for 5-level paging (vm->va_bits == 57),
+                * it doesn't take effect unless a CR4.LA57 is set, which it
+                * isn't for this VM_MODE.
+                */
+               TEST_ASSERT(vm->va_bits == 48 || vm->va_bits == 57,
+                           "Linear address width (%d bits) not supported",
+                           vm->va_bits);
                pr_debug("Guest physical address width detected: %d\n",
                         vm->pa_bits);
                vm->pgtable_levels = 4;
+               vm->va_bits = 48;
 #else
                TEST_FAIL("VM_MODE_PXXV48_4K not supported on non-x86 platforms");
 #endif