We're removing struct clk from the clk provider API, so switch
this code to using the clk_hw based provider APIs.
Cc: Wentao Xu <wentaox@codeaurora.org>
Cc: Rob Clark <robdclark@gmail.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
        cached_state->postdiv1 =
                        pll_read(base + REG_DSI_28nm_PHY_PLL_POSTDIV1_CFG);
        cached_state->byte_mux = pll_read(base + REG_DSI_28nm_PHY_PLL_VREG_CFG);
-       cached_state->vco_rate = __clk_get_rate(pll->clk_hw.clk);
+       cached_state->vco_rate = clk_hw_get_rate(&pll->clk_hw);
 }
 
 static int dsi_pll_28nm_restore_state(struct msm_dsi_pll *pll)
        int ret;
 
        if ((cached_state->vco_rate != 0) &&
-               (cached_state->vco_rate == __clk_get_rate(pll->clk_hw.clk))) {
+               (cached_state->vco_rate == clk_hw_get_rate(&pll->clk_hw))) {
                ret = dsi_pll_28nm_clk_set_rate(&pll->clk_hw,
                                                cached_state->vco_rate, 0);
                if (ret) {