DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 15)),
 };
 
+static const struct dpu_dsc_cfg msm8998_dsc[] = {
+       DSC_BLK("dsc_0", DSC_0, 0x80000, 0),
+       DSC_BLK("dsc_1", DSC_1, 0x80400, 0),
+};
+
 static const struct dpu_dspp_cfg msm8998_dspp[] = {
        DSPP_BLK("dspp_0", DSPP_0, 0x54000, DSPP_SC7180_MASK,
                 &msm8998_dspp_sblk),
        .dspp = msm8998_dspp,
        .pingpong_count = ARRAY_SIZE(msm8998_pp),
        .pingpong = msm8998_pp,
+       .dsc_count = ARRAY_SIZE(msm8998_dsc),
+       .dsc = msm8998_dsc,
        .intf_count = ARRAY_SIZE(msm8998_intf),
        .intf = msm8998_intf,
        .vbif_count = ARRAY_SIZE(msm8998_vbif),