a certain pin config setting. Look in e.g. ``<linux/pinctrl/pinconf-generic.h>``
and you find this in the documentation:
- PIN_CONFIG_OUTPUT:
+ PIN_CONFIG_LEVEL:
this will configure the pin in output, use argument
1 to indicate high level, argument 0 to indicate low level.
};
static unsigned long uart_sleep_mode[] = {
- PIN_CONF_PACKED(PIN_CONFIG_OUTPUT, 0),
+ PIN_CONF_PACKED(PIN_CONFIG_LEVEL, 0),
};
static struct pinctrl_map pinmap[] __initdata = {
list_del(&cfg->head);
switch (cfg->param) {
- case PIN_CONFIG_OUTPUT:
+ case PIN_CONFIG_LEVEL:
ret = rockchip_gpio_direction_output(&bank->gpio_chip, cfg->pin, cfg->arg);
if (ret)
dev_warn(dev, "setting output pin %u to %u failed\n", cfg->pin,
/* No way to read back bias config in HW */
switch (param) {
- case PIN_CONFIG_OUTPUT:
+ case PIN_CONFIG_LEVEL:
if (fsel != BCM2835_FSEL_GPIO_OUT)
return -EINVAL;
break;
/* Set output-high or output-low */
- case PIN_CONFIG_OUTPUT:
+ case PIN_CONFIG_LEVEL:
bcm2835_gpio_set_bit(pc, arg ? GPSET0 : GPCLR0, pin);
break;
break;
/* Set output-high or output-low */
- case PIN_CONFIG_OUTPUT:
+ case PIN_CONFIG_LEVEL:
bcm2835_gpio_set_bit(pc, arg ? GPSET0 : GPCLR0, pin);
break;
if (conf[0] & MADERA_GP1_IP_CFG_MASK)
result = 1;
break;
- case PIN_CONFIG_OUTPUT:
+ case PIN_CONFIG_LEVEL:
if ((conf[1] & MADERA_GP1_DIR_MASK) &&
(conf[0] & MADERA_GP1_LVL_MASK))
result = 1;
mask[1] |= MADERA_GP1_DIR_MASK;
conf[1] |= MADERA_GP1_DIR;
break;
- case PIN_CONFIG_OUTPUT:
+ case PIN_CONFIG_LEVEL:
val = pinconf_to_config_argument(*configs);
mask[0] |= MADERA_GP1_LVL_MASK;
if (val)
break;
case PIN_CONFIG_OUTPUT_ENABLE:
case PIN_CONFIG_INPUT_ENABLE:
- case PIN_CONFIG_OUTPUT: {
+ case PIN_CONFIG_LEVEL: {
bool input = param == PIN_CONFIG_INPUT_ENABLE;
int err;
if (err)
return err;
- if (param == PIN_CONFIG_OUTPUT) {
+ if (param == PIN_CONFIG_LEVEL) {
err = airoha_pinconf_set_pin_value(pctrl_dev,
pin, !!arg);
if (err)
goto err;
break;
- case PIN_CONFIG_OUTPUT:
+ case PIN_CONFIG_LEVEL:
err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DIR,
MTK_OUTPUT);
if (err)
mtk_pmx_gpio_set_direction(pctldev, NULL, pin, true);
ret = mtk_pconf_set_ies_smt(pctl, pin, arg, param);
break;
- case PIN_CONFIG_OUTPUT:
+ case PIN_CONFIG_LEVEL:
mtk_gpio_set(pctl->chip, pin, arg);
ret = mtk_pmx_gpio_set_direction(pctldev, NULL, pin, false);
break;
if (!ret)
err = -EINVAL;
break;
- case PIN_CONFIG_OUTPUT:
+ case PIN_CONFIG_LEVEL:
err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_DIR, &ret);
if (err)
break;
/* regard all non-zero value as enable */
err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_SR, !!arg);
break;
- case PIN_CONFIG_OUTPUT:
+ case PIN_CONFIG_LEVEL:
err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DO,
arg);
if (err)
return -EINVAL;
arg = 1;
break;
- case PIN_CONFIG_OUTPUT:
+ case PIN_CONFIG_LEVEL:
ret = aml_pinconf_get_output(info, pin);
if (ret <= 0)
return -EINVAL;
switch (param) {
case PIN_CONFIG_DRIVE_STRENGTH_UA:
case PIN_CONFIG_OUTPUT_ENABLE:
- case PIN_CONFIG_OUTPUT:
+ case PIN_CONFIG_LEVEL:
arg = pinconf_to_config_argument(configs[i]);
break;
case PIN_CONFIG_OUTPUT_ENABLE:
ret = aml_pinconf_set_output(info, pin, arg);
break;
- case PIN_CONFIG_OUTPUT:
+ case PIN_CONFIG_LEVEL:
ret = aml_pinconf_set_output_drive(info, pin, arg);
break;
default:
switch (param) {
case PIN_CONFIG_DRIVE_STRENGTH_UA:
case PIN_CONFIG_OUTPUT_ENABLE:
- case PIN_CONFIG_OUTPUT:
+ case PIN_CONFIG_LEVEL:
arg = pinconf_to_config_argument(configs[i]);
break;
case PIN_CONFIG_OUTPUT_ENABLE:
ret = meson_pinconf_set_output(pc, pin, arg);
break;
- case PIN_CONFIG_OUTPUT:
+ case PIN_CONFIG_LEVEL:
ret = meson_pinconf_set_output_drive(pc, pin, arg);
break;
default:
return -EINVAL;
arg = 1;
break;
- case PIN_CONFIG_OUTPUT:
+ case PIN_CONFIG_LEVEL:
ret = meson_pinconf_get_output(pc, pin);
if (ret <= 0)
return -EINVAL;
dev_dbg(chip->parent, "pin %d [%#lx]: %s %s\n",
pin, configs[i],
- (param == PIN_CONFIG_OUTPUT) ? "output " : "input",
- (param == PIN_CONFIG_OUTPUT) ?
+ (param == PIN_CONFIG_LEVEL) ? "output " : "input",
+ (param == PIN_CONFIG_LEVEL) ?
str_high_low(argument) :
(argument ? "pull up" : "pull down"));
ret = abx500_gpio_direction_input(chip, offset);
break;
- case PIN_CONFIG_OUTPUT:
+ case PIN_CONFIG_LEVEL:
ret = abx500_gpio_direction_output(chip, offset,
argument);
break;
else if (param == PIN_CONFIG_BIAS_PULL_DOWN)
rc = (!pu && pd);
break;
- case PIN_CONFIG_OUTPUT:
+ case PIN_CONFIG_LEVEL:
case PIN_CONFIG_INPUT_ENABLE:
ie = ioread32(bank->base + NPCM7XX_GP_N_IEM) & pinmask;
oe = ioread32(bank->base + NPCM7XX_GP_N_OE) & pinmask;
if (param == PIN_CONFIG_INPUT_ENABLE)
rc = (ie && !oe);
- else if (param == PIN_CONFIG_OUTPUT)
+ else if (param == PIN_CONFIG_LEVEL)
rc = (!ie && oe);
break;
case PIN_CONFIG_DRIVE_PUSH_PULL:
iowrite32(gpio, bank->base + NPCM7XX_GP_N_OEC);
bank->direction_input(&bank->chip.gc, pin % bank->chip.gc.ngpio);
break;
- case PIN_CONFIG_OUTPUT:
+ case PIN_CONFIG_LEVEL:
bank->direction_output(&bank->chip.gc, pin % bank->chip.gc.ngpio, arg);
iowrite32(gpio, bank->base + NPCM7XX_GP_N_OES);
break;
else if (param == PIN_CONFIG_BIAS_PULL_DOWN)
rc = !pu && pd;
break;
- case PIN_CONFIG_OUTPUT:
+ case PIN_CONFIG_LEVEL:
case PIN_CONFIG_INPUT_ENABLE:
ie = ioread32(bank->base + NPCM8XX_GP_N_IEM) & pinmask;
oe = ioread32(bank->base + NPCM8XX_GP_N_OE) & pinmask;
if (param == PIN_CONFIG_INPUT_ENABLE)
rc = (ie && !oe);
- else if (param == PIN_CONFIG_OUTPUT)
+ else if (param == PIN_CONFIG_LEVEL)
rc = (!ie && oe);
break;
case PIN_CONFIG_DRIVE_PUSH_PULL:
iowrite32(gpio, bank->base + NPCM8XX_GP_N_OEC);
bank->direction_input(&bank->chip.gc, pin % bank->chip.gc.ngpio);
break;
- case PIN_CONFIG_OUTPUT:
+ case PIN_CONFIG_LEVEL:
bank->direction_output(&bank->chip.gc, pin % bank->chip.gc.ngpio, arg);
iowrite32(gpio, bank->base + NPCM8XX_GP_N_OES);
break;
PCONFDUMP(PIN_CONFIG_INPUT_SCHMITT_ENABLE, "input schmitt enabled", NULL, false),
PCONFDUMP(PIN_CONFIG_MODE_LOW_POWER, "pin low power", "mode", true),
PCONFDUMP(PIN_CONFIG_OUTPUT_ENABLE, "output enabled", NULL, false),
- PCONFDUMP(PIN_CONFIG_OUTPUT, "pin output", "level", true),
+ PCONFDUMP(PIN_CONFIG_LEVEL, "pin output", "level", true),
PCONFDUMP(PIN_CONFIG_OUTPUT_IMPEDANCE_OHMS, "output impedance", "ohms", true),
PCONFDUMP(PIN_CONFIG_POWER_SOURCE, "pin power source", "selector", true),
PCONFDUMP(PIN_CONFIG_SLEEP_HARDWARE_STATE, "sleep hardware state", NULL, false),
{ "low-power-enable", PIN_CONFIG_MODE_LOW_POWER, 1 },
{ "output-disable", PIN_CONFIG_OUTPUT_ENABLE, 0 },
{ "output-enable", PIN_CONFIG_OUTPUT_ENABLE, 1 },
- { "output-high", PIN_CONFIG_OUTPUT, 1, },
+ { "output-high", PIN_CONFIG_LEVEL, 1, },
{ "output-impedance-ohms", PIN_CONFIG_OUTPUT_IMPEDANCE_OHMS, 0 },
- { "output-low", PIN_CONFIG_OUTPUT, 0, },
+ { "output-low", PIN_CONFIG_LEVEL, 0, },
{ "power-source", PIN_CONFIG_POWER_SOURCE, 0 },
{ "sleep-hardware-state", PIN_CONFIG_SLEEP_HARDWARE_STATE, 0 },
{ "slew-rate", PIN_CONFIG_SLEW_RATE, 0 },
conf |= ATMEL_PIO_IFSCEN_MASK;
}
break;
- case PIN_CONFIG_OUTPUT:
+ case PIN_CONFIG_LEVEL:
conf |= ATMEL_PIO_DIR_MASK;
bank = ATMEL_PIO_BANK(pin_id);
pin = ATMEL_PIO_LINE(pin_id);
case PIN_CONFIG_OUTPUT_ENABLE:
reg = AW9523_REG_CONF_STATE(pin);
break;
- case PIN_CONFIG_OUTPUT:
+ case PIN_CONFIG_LEVEL:
reg = AW9523_REG_OUT_STATE(pin);
break;
default:
switch (param) {
case PIN_CONFIG_BIAS_PULL_UP:
case PIN_CONFIG_INPUT_ENABLE:
- case PIN_CONFIG_OUTPUT:
+ case PIN_CONFIG_LEVEL:
val &= BIT(regbit);
break;
case PIN_CONFIG_BIAS_PULL_DOWN:
goto end;
switch (param) {
- case PIN_CONFIG_OUTPUT:
+ case PIN_CONFIG_LEVEL:
/* First, enable pin output */
rc = regmap_update_bits(awi->regmap,
AW9523_REG_CONF_STATE(pin),
case PIN_CONFIG_MODE_PWM:
reg = CY8C95X0_SELPWM;
break;
- case PIN_CONFIG_OUTPUT:
+ case PIN_CONFIG_LEVEL:
reg = CY8C95X0_OUTPUT;
break;
case PIN_CONFIG_OUTPUT_ENABLE:
case PIN_CONFIG_BIAS_PULL_UP:
case PIN_CONFIG_BIAS_PULL_DOWN:
case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
- case PIN_CONFIG_OUTPUT:
+ case PIN_CONFIG_LEVEL:
case PIN_CONFIG_SLEW_RATE:
continue;
default:
ingenic_set_schmitt_trigger(jzpc, pin, arg);
break;
- case PIN_CONFIG_OUTPUT:
+ case PIN_CONFIG_LEVEL:
ret = pinctrl_gpio_direction_output(jzpc->gc,
pin - jzpc->gc->base);
if (ret)
else
val &= ~K210_PC_ST;
break;
- case PIN_CONFIG_OUTPUT:
+ case PIN_CONFIG_LEVEL:
k210_pinmux_set_pin_function(pctldev, pin, K210_PCF_CONSTANT);
val = readl(&pdata->fpioa->pins[pin]);
val |= K210_PC_MODE_OUT;
val = !bank->is_input;
break;
- case PIN_CONFIG_OUTPUT:
+ case PIN_CONFIG_LEVEL:
if (bank->is_input)
return -EINVAL;
val = sgpio_output_get(priv, &addr);
arg = pinconf_to_config_argument(configs[cfg]);
switch (param) {
- case PIN_CONFIG_OUTPUT:
+ case PIN_CONFIG_LEVEL:
if (bank->is_input)
return -EINVAL;
err = sgpio_output_set(priv, &addr, arg);
return err;
break;
- case PIN_CONFIG_OUTPUT:
+ case PIN_CONFIG_LEVEL:
err = regmap_read(info->map, REG(OCELOT_GPIO_OUT, info, pin),
&val);
if (err)
case PIN_CONFIG_OUTPUT_ENABLE:
case PIN_CONFIG_INPUT_ENABLE:
- case PIN_CONFIG_OUTPUT:
+ case PIN_CONFIG_LEVEL:
p = pin % 32;
if (arg)
regmap_write(info->map,
case PIN_CONFIG_INPUT_ENABLE:
arg = !!(readl(bank->reg_base + TRIS_REG) & mask);
break;
- case PIN_CONFIG_OUTPUT:
+ case PIN_CONFIG_LEVEL:
arg = !(readl(bank->reg_base + TRIS_REG) & mask);
break;
default:
case PIN_CONFIG_INPUT_ENABLE:
pic32_gpio_direction_input(&bank->gpio_chip, offset);
break;
- case PIN_CONFIG_OUTPUT:
+ case PIN_CONFIG_LEVEL:
pic32_gpio_direction_output(&bank->gpio_chip,
offset, arg);
break;
u32 arg = 0;
switch (param) {
- case PIN_CONFIG_OUTPUT:
+ case PIN_CONFIG_LEVEL:
case PIN_CONFIG_INPUT_ENABLE:
arg = rk805_gpio_get(&pci->gpio_chip, pin);
break;
arg = pinconf_to_config_argument(configs[i]);
switch (param) {
- case PIN_CONFIG_OUTPUT:
+ case PIN_CONFIG_LEVEL:
rk805_gpio_set(&pci->gpio_chip, pin, arg);
rk805_pmx_gpio_set_direction(pctldev, NULL, pin, false);
break;
param = pinconf_to_config_param(configs[i]);
arg = pinconf_to_config_argument(configs[i]);
- if (param == PIN_CONFIG_OUTPUT || param == PIN_CONFIG_INPUT_ENABLE) {
+ if (param == PIN_CONFIG_LEVEL || param == PIN_CONFIG_INPUT_ENABLE) {
/*
* Check for gpio driver not being probed yet.
* The lock makes sure that either gpio-probe has completed
if (rc)
return rc;
break;
- case PIN_CONFIG_OUTPUT:
+ case PIN_CONFIG_LEVEL:
rc = rockchip_set_mux(bank, pin - bank->pin_base,
RK_FUNC_GPIO);
if (rc != RK_FUNC_GPIO)
arg = 1;
break;
- case PIN_CONFIG_OUTPUT:
+ case PIN_CONFIG_LEVEL:
rc = rockchip_get_mux(bank, pin - bank->pin_base);
if (rc != RK_FUNC_GPIO)
return -EINVAL;
rp1_output_enable(pin, arg);
break;
- case PIN_CONFIG_OUTPUT:
+ case PIN_CONFIG_LEVEL:
rp1_set_value(pin, arg);
rp1_set_dir(pin, RP1_DIR_OUTPUT);
rp1_set_fsel(pin, RP1_FSEL_GPIO);
case PIN_CONFIG_MODE_LOW_POWER:
*type = SCMI_PIN_LOW_POWER_MODE;
break;
- case PIN_CONFIG_OUTPUT:
+ case PIN_CONFIG_LEVEL:
*type = SCMI_PIN_OUTPUT_VALUE;
break;
case PIN_CONFIG_OUTPUT_ENABLE:
if ((!dir && !type) || (dir && type))
arg = 1;
break;
- case PIN_CONFIG_OUTPUT:
+ case PIN_CONFIG_LEVEL:
if (dir)
return -EINVAL;
if (ret)
return ret;
break;
- case PIN_CONFIG_OUTPUT:
+ case PIN_CONFIG_LEVEL:
ret = stmfx_gpio_direction_output(&pctl->gpio_chip,
pin, arg);
if (ret)
if (sx150x_pin_is_oscio(pctl, pin)) {
switch (param) {
case PIN_CONFIG_DRIVE_PUSH_PULL:
- case PIN_CONFIG_OUTPUT:
+ case PIN_CONFIG_LEVEL:
ret = regmap_read(pctl->regmap,
pctl->data->pri.x789.reg_clock,
&data);
}
break;
- case PIN_CONFIG_OUTPUT:
+ case PIN_CONFIG_LEVEL:
ret = sx150x_gpio_get_direction(&pctl->gpio, pin);
if (ret < 0)
return ret;
arg = pinconf_to_config_argument(configs[i]);
if (sx150x_pin_is_oscio(pctl, pin)) {
- if (param == PIN_CONFIG_OUTPUT) {
+ if (param == PIN_CONFIG_LEVEL) {
ret = sx150x_gpio_direction_output(&pctl->gpio,
pin, arg);
if (ret < 0)
break;
- case PIN_CONFIG_OUTPUT:
+ case PIN_CONFIG_LEVEL:
ret = sx150x_gpio_direction_output(&pctl->gpio,
pin, arg);
if (ret < 0)
arg = 1;
break;
case PIN_CONFIG_INPUT_ENABLE:
- case PIN_CONFIG_OUTPUT:
+ case PIN_CONFIG_LEVEL:
if (is_out)
arg = 1;
break;
case PIN_CONFIG_INPUT_ENABLE:
output_enabled = false;
break;
- case PIN_CONFIG_OUTPUT:
+ case PIN_CONFIG_LEVEL:
output_enabled = true;
value = arg;
break;
struct lpi_pinctrl *state = gpiochip_get_data(chip);
unsigned long config;
- config = pinconf_to_config_packed(PIN_CONFIG_OUTPUT, val);
+ config = pinconf_to_config_packed(PIN_CONFIG_LEVEL, val);
return lpi_config_set(state->ctrl, pin, &config, 1);
}
struct lpi_pinctrl *state = gpiochip_get_data(chip);
unsigned long config;
- config = pinconf_to_config_packed(PIN_CONFIG_OUTPUT, value);
+ config = pinconf_to_config_packed(PIN_CONFIG_LEVEL, value);
return lpi_config_set(state->ctrl, pin, &config, 1);
}
*bit = g->drv_bit;
*mask = 7;
break;
- case PIN_CONFIG_OUTPUT:
+ case PIN_CONFIG_LEVEL:
case PIN_CONFIG_INPUT_ENABLE:
case PIN_CONFIG_OUTPUT_ENABLE:
*bit = g->oe_bit;
case PIN_CONFIG_DRIVE_STRENGTH:
arg = msm_regval_to_drive(arg);
break;
- case PIN_CONFIG_OUTPUT:
+ case PIN_CONFIG_LEVEL:
/* Pin is not output */
if (!arg)
return -EINVAL;
else
arg = (arg / 2) - 1;
break;
- case PIN_CONFIG_OUTPUT:
+ case PIN_CONFIG_LEVEL:
/* set output value */
raw_spin_lock_irqsave(&pctrl->lock, flags);
val = msm_readl_io(pctrl, g);
case PIN_CONFIG_OUTPUT_ENABLE:
arg = pad->output_enabled;
break;
- case PIN_CONFIG_OUTPUT:
+ case PIN_CONFIG_LEVEL:
arg = pad->out_value;
break;
case PMIC_GPIO_CONF_PULL_UP:
case PIN_CONFIG_OUTPUT_ENABLE:
pad->output_enabled = arg ? true : false;
break;
- case PIN_CONFIG_OUTPUT:
+ case PIN_CONFIG_LEVEL:
pad->output_enabled = true;
pad->out_value = arg;
break;
struct pmic_gpio_state *state = gpiochip_get_data(chip);
unsigned long config;
- config = pinconf_to_config_packed(PIN_CONFIG_OUTPUT, val);
+ config = pinconf_to_config_packed(PIN_CONFIG_LEVEL, val);
return pmic_gpio_config_set(state->ctrl, pin, &config, 1);
}
struct pmic_gpio_state *state = gpiochip_get_data(chip);
unsigned long config;
- config = pinconf_to_config_packed(PIN_CONFIG_OUTPUT, value);
+ config = pinconf_to_config_packed(PIN_CONFIG_LEVEL, value);
return pmic_gpio_config_set(state->ctrl, pin, &config, 1);
}
return -EINVAL;
arg = 1;
break;
- case PIN_CONFIG_OUTPUT:
+ case PIN_CONFIG_LEVEL:
arg = pad->out_value;
break;
case PMIC_MPP_CONF_DTEST_SELECTOR:
case PIN_CONFIG_INPUT_ENABLE:
pad->input_enabled = arg ? true : false;
break;
- case PIN_CONFIG_OUTPUT:
+ case PIN_CONFIG_LEVEL:
pad->output_enabled = true;
pad->out_value = arg;
break;
struct pmic_mpp_state *state = gpiochip_get_data(chip);
unsigned long config;
- config = pinconf_to_config_packed(PIN_CONFIG_OUTPUT, val);
+ config = pinconf_to_config_packed(PIN_CONFIG_LEVEL, val);
return pmic_mpp_config_set(state->ctrl, pin, &config, 1);
}
struct pmic_mpp_state *state = gpiochip_get_data(chip);
unsigned long config;
- config = pinconf_to_config_packed(PIN_CONFIG_OUTPUT, value);
+ config = pinconf_to_config_packed(PIN_CONFIG_LEVEL, value);
return pmic_mpp_config_set(state->ctrl, pin, &config, 1);
}
return -EINVAL;
arg = 1;
break;
- case PIN_CONFIG_OUTPUT:
+ case PIN_CONFIG_LEVEL:
if (pin->mode & PM8XXX_GPIO_MODE_OUTPUT)
arg = pin->output_value;
else
pin->mode = PM8XXX_GPIO_MODE_INPUT;
banks |= BIT(0) | BIT(1);
break;
- case PIN_CONFIG_OUTPUT:
+ case PIN_CONFIG_LEVEL:
pin->mode = PM8XXX_GPIO_MODE_OUTPUT;
pin->output_value = !!arg;
banks |= BIT(0) | BIT(1);
case PIN_CONFIG_INPUT_ENABLE:
arg = pin->input;
break;
- case PIN_CONFIG_OUTPUT:
+ case PIN_CONFIG_LEVEL:
arg = pin->output_value;
break;
case PIN_CONFIG_POWER_SOURCE:
case PIN_CONFIG_INPUT_ENABLE:
pin->input = true;
break;
- case PIN_CONFIG_OUTPUT:
+ case PIN_CONFIG_LEVEL:
pin->output = true;
pin->output_value = !!arg;
break;
case PIN_CONFIG_INPUT_ENABLE:
pinmux_flags |= MUX_FLAGS_SWIO_INPUT;
break;
- case PIN_CONFIG_OUTPUT: /* for DT backwards compatibility */
+ case PIN_CONFIG_LEVEL: /* for DT backwards compatibility */
case PIN_CONFIG_OUTPUT_ENABLE:
pinmux_flags |= MUX_FLAGS_SWIO_OUTPUT;
break;
case PIN_CONFIG_BIAS_PULL_DOWN:
ret = stm32_pconf_set_bias(bank, offset, 2);
break;
- case PIN_CONFIG_OUTPUT:
+ case PIN_CONFIG_LEVEL:
__stm32_gpio_set(bank, offset, arg);
ret = stm32_pmx_gpio_set_direction(pctldev, range, pin, false);
break;
case PIN_CONFIG_INPUT_ENABLE:
break;
- case PIN_CONFIG_OUTPUT:
+ case PIN_CONFIG_LEVEL:
return sppctl_gpio_direction_output(chip, offset, 0);
case PIN_CONFIG_PERSIST_STATE:
arg = 0;
break;
- case PIN_CONFIG_OUTPUT:
+ case PIN_CONFIG_LEVEL:
if (!sppctl_first_get(&pctl->spp_gchip->chip, pin))
return -EINVAL;
if (!sppctl_master_get(&pctl->spp_gchip->chip, pin))
* passed in the argument on a custom form, else just use argument 1
* to indicate low power mode, argument 0 turns low power mode off.
* @PIN_CONFIG_MODE_PWM: this will configure the pin for PWM
- * @PIN_CONFIG_OUTPUT: this will configure the pin as an output and drive a
- * value on the line. Use argument 1 to indicate high level, argument 0 to
- * indicate low level. (Please see Documentation/driver-api/pin-control.rst,
+ * @PIN_CONFIG_LEVEL: setting this will configure the pin as an output and
+ * drive a value on the line. Use argument 1 to indicate high level,
+ * argument 0 to indicate low level. Conversely the value of the line
+ * can be read using this parameter, if and only if that value can be
+ * represented as a binary 0 or 1 where 0 indicate a low voltage level
+ * and 1 indicate a high voltage level.
+ * (Please see Documentation/driver-api/pin-control.rst,
* section "GPIO mode pitfalls" for a discussion around this parameter.)
* @PIN_CONFIG_OUTPUT_ENABLE: this will enable the pin's output mode
* without driving a value there. For most platforms this reduces to
PIN_CONFIG_INPUT_SCHMITT_UV,
PIN_CONFIG_MODE_LOW_POWER,
PIN_CONFIG_MODE_PWM,
- PIN_CONFIG_OUTPUT,
+ PIN_CONFIG_LEVEL,
PIN_CONFIG_OUTPUT_ENABLE,
PIN_CONFIG_OUTPUT_IMPEDANCE_OHMS,
PIN_CONFIG_PERSIST_STATE,
unsigned long config)
{
switch (pinconf_to_config_param(config)) {
- case PIN_CONFIG_OUTPUT:
+ case PIN_CONFIG_LEVEL:
case PIN_CONFIG_OUTPUT_ENABLE:
return -EOPNOTSUPP;
default: