pinctrl: intel: Use same order of bit fields for PADCFG2

PADCFG0 and PADCFG1 are ordered from MSB to LSB, do the same
for PADCFG2 bit fields. No functional changes intended.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>

diff --git a/drivers/pinctrl/intel/pinctrl-intel.c b/drivers/pinctrl/intel/pinctrl-intel.c
index ad32e3cfb4a7ba267d7fa31dd6102aa70f7e0f2c..038a5721ae52106825f78c42f248394883c6744c 100644 (file)
--- a/drivers/pinctrl/intel/pinctrl-intel.c
+++ b/drivers/pinctrl/intel/pinctrl-intel.c
@@ -88,9 +88,9 @@
 #define PADCFG1_TERM_800               (BIT(2) | BIT(1) | BIT(0))
 
 #define PADCFG2                                0x008
-#define PADCFG2_DEBEN                  BIT(0)
 #define PADCFG2_DEBOUNCE_SHIFT         1
 #define PADCFG2_DEBOUNCE_MASK          GENMASK(4, 1)
+#define PADCFG2_DEBEN                  BIT(0)
 
 #define DEBOUNCE_PERIOD_NSEC           31250