media: verisilicon: AV1: Correct some sizes/positions on register fields

Some fields aren't well positioned or with an incorrect size inside the
hardware registers. Fix them.

This doesn't impact the Fluster score.

Fixes: 727a400686a2 ("media: verisilicon: Add Rockchip AV1 decoder")
Signed-off-by: Benjamin Gaignard <benjamin.gaignard@collabora.com>
Reviewed-by: Nicolas Dufresne <nicolas.dufresne@collabora.com>
Signed-off-by: Sebastian Fricke <sebastian.fricke@collabora.com>
Signed-off-by: Hans Verkuil <hverkuil-cisco@xs4all.nl>

diff --git a/drivers/media/platform/verisilicon/rockchip_vpu981_regs.h b/drivers/media/platform/verisilicon/rockchip_vpu981_regs.h
index 850ff0f844248d7b74b5dc1aa84356531ff25d58..e4008da64f19b8408302b773d8e37fd3e5441375 100644 (file)
--- a/drivers/media/platform/verisilicon/rockchip_vpu981_regs.h
+++ b/drivers/media/platform/verisilicon/rockchip_vpu981_regs.h
@@ -327,7 +327,7 @@
 
 #define av1_apf_threshold              AV1_DEC_REG(55, 0, 0xffff)
 #define av1_apf_single_pu_mode         AV1_DEC_REG(55, 30, 0x1)
-#define av1_apf_disable                        AV1_DEC_REG(55, 30, 0x1)
+#define av1_apf_disable                        AV1_DEC_REG(55, 31, 0x1)
 
 #define av1_dec_max_burst              AV1_DEC_REG(58, 0, 0xff)
 #define av1_dec_buswidth               AV1_DEC_REG(58, 8, 0x7)
@@ -337,10 +337,10 @@
 #define av1_dec_mc_polltime            AV1_DEC_REG(58, 17, 0x3ff)
 #define av1_dec_mc_pollmode            AV1_DEC_REG(58, 27, 0x3)
 
-#define av1_filt_ref_adj_3             AV1_DEC_REG(59, 0, 0x3f)
-#define av1_filt_ref_adj_2             AV1_DEC_REG(59, 7, 0x3f)
-#define av1_filt_ref_adj_1             AV1_DEC_REG(59, 14, 0x3f)
-#define av1_filt_ref_adj_0             AV1_DEC_REG(59, 21, 0x3f)
+#define av1_filt_ref_adj_3             AV1_DEC_REG(59, 0, 0x7f)
+#define av1_filt_ref_adj_2             AV1_DEC_REG(59, 7, 0x7f)
+#define av1_filt_ref_adj_1             AV1_DEC_REG(59, 14, 0x7f)
+#define av1_filt_ref_adj_0             AV1_DEC_REG(59, 21, 0x7f)
 #define av1_ref0_sign_bias             AV1_DEC_REG(59, 28, 0x1)
 #define av1_ref1_sign_bias             AV1_DEC_REG(59, 29, 0x1)
 #define av1_ref2_sign_bias             AV1_DEC_REG(59, 30, 0x1)