]> www.infradead.org Git - users/hch/configfs.git/commitdiff
drm/xe/xe2: Introduce performance changes
authorAkshata Jahagirdar <akshata.jahagirdar@intel.com>
Fri, 2 Aug 2024 14:12:03 +0000 (07:12 -0700)
committerMatt Roper <matthew.d.roper@intel.com>
Fri, 2 Aug 2024 21:31:04 +0000 (14:31 -0700)
Add Compression Performance Improvement Changes in Xe2

v2: Rebase

v3: Rebase, updated as per latest changes on bspec,
    Removed unnecessary default actions (Matt)
    formatting nits (Tejas)

v4: Formatting nits, removed default set action for bit 14 (Matt)

Bspec: 72161
Signed-off-by: Akshata Jahagirdar <akshata.jahagirdar@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/c2dd753fdc55df6a6432026f2df9c2684a0d25c1.1722607628.git.akshata.jahagirdar@intel.com
drivers/gpu/drm/xe/regs/xe_gt_regs.h
drivers/gpu/drm/xe/xe_tuning.c

index 3b87f95f9ecfe5e2a5a29e0cd17d426b3772f71e..c50643ab4c844ffef9ad086e992f8c5de771b331 100644 (file)
 #define XEHP_L3NODEARBCFG                      XE_REG_MCR(0xb0b4)
 #define   XEHP_LNESPARE                                REG_BIT(19)
 
+#define L3SQCREG2                              XE_REG_MCR(0xb104)
+#define   COMPMEMRD256BOVRFETCHEN              REG_BIT(20)
+
 #define L3SQCREG3                              XE_REG_MCR(0xb108)
 #define   COMPPWOVERFETCHEN                    REG_BIT(28)
 
index 77d4eec0118d442c23953dc83f9927d10c955fa4..3817b7743b0ca452b04a3383aa0fcda6d915e995 100644 (file)
@@ -45,6 +45,11 @@ static const struct xe_rtp_entry_sr gt_tunings[] = {
          XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, XE_RTP_END_VERSION_UNDEFINED)),
          XE_RTP_ACTIONS(SET(L3SQCREG3, COMPPWOVERFETCHEN))
        },
+       { XE_RTP_NAME("Tuning: L2 Overfetch Compressible Only"),
+         XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, XE_RTP_END_VERSION_UNDEFINED)),
+         XE_RTP_ACTIONS(SET(L3SQCREG2,
+                            COMPMEMRD256BOVRFETCHEN))
+       },
        {}
 };