if (port) {
                clk_prepare_enable(ourport->clk);
+               if (!IS_ERR(ourport->baudclk))
+                       clk_prepare_enable(ourport->baudclk);
                s3c24xx_serial_resetport(port, s3c24xx_port_to_cfg(port));
+               if (!IS_ERR(ourport->baudclk))
+                       clk_disable_unprepare(ourport->baudclk);
                clk_disable_unprepare(ourport->clk);
 
                uart_resume_port(&s3c24xx_uart_drv, port);
                        if (rx_enabled(port))
                                uintm &= ~S3C64XX_UINTM_RXD_MSK;
                        clk_prepare_enable(ourport->clk);
+                       if (!IS_ERR(ourport->baudclk))
+                               clk_prepare_enable(ourport->baudclk);
                        wr_regl(port, S3C64XX_UINTM, uintm);
+                       if (!IS_ERR(ourport->baudclk))
+                               clk_disable_unprepare(ourport->baudclk);
                        clk_disable_unprepare(ourport->clk);
                }
        }