ARM: imx6q: add spdif gate clock

It adds the missing spdif gate clock into imx6q clock driver.

Signed-off-by: Shawn Guo <shawn.guo@linaro.org>

diff --git a/Documentation/devicetree/bindings/clock/imx6q-clock.txt b/Documentation/devicetree/bindings/clock/imx6q-clock.txt
index a0e104f0527e058843c1f01a33997ff64d8f37cb..794d089aecf7992573bd06e1e18d1b14bcb1ca96 100644 (file)
--- a/Documentation/devicetree/bindings/clock/imx6q-clock.txt
+++ b/Documentation/devicetree/bindings/clock/imx6q-clock.txt
@@ -209,6 +209,7 @@ clocks and IDs.
        pll5_post_div           194
        pll5_video_div          195
        eim_slow                196
+       spdif                   197
 
 Examples:
 

diff --git a/arch/arm/mach-imx/clk-imx6q.c b/arch/arm/mach-imx/clk-imx6q.c
index db9f8f5646f1a778b7d29cae1f4e440a015f97a6..d739df196a15a3cf946145167c7de378ee15627d 100644 (file)
--- a/arch/arm/mach-imx/clk-imx6q.c
+++ b/arch/arm/mach-imx/clk-imx6q.c
@@ -239,7 +239,8 @@ enum mx6q_clks {
        pll4_audio, pll5_video, pll8_mlb, pll7_usb_host, pll6_enet, ssi1_ipg,
        ssi2_ipg, ssi3_ipg, rom, usbphy1, usbphy2, ldb_di0_div_3_5, ldb_di1_div_3_5,
        sata_ref, sata_ref_100m, pcie_ref, pcie_ref_125m, enet_ref, usbphy1_gate,
-       usbphy2_gate, pll4_post_div, pll5_post_div, pll5_video_div, eim_slow, clk_max
+       usbphy2_gate, pll4_post_div, pll5_post_div, pll5_video_div, eim_slow,
+       spdif, clk_max
 };
 
 static struct clk *clk[clk_max];
@@ -521,6 +522,7 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)
        clk[sata]         = imx_clk_gate2("sata",          "ipg",               base + 0x7c, 4);
        clk[sdma]         = imx_clk_gate2("sdma",          "ahb",               base + 0x7c, 6);
        clk[spba]         = imx_clk_gate2("spba",          "ipg",               base + 0x7c, 12);
+       clk[spdif]        = imx_clk_gate2("spdif",         "spdif_podf",        base + 0x7c, 14);
        clk[ssi1_ipg]     = imx_clk_gate2("ssi1_ipg",      "ipg",               base + 0x7c, 18);
        clk[ssi2_ipg]     = imx_clk_gate2("ssi2_ipg",      "ipg",               base + 0x7c, 20);
        clk[ssi3_ipg]     = imx_clk_gate2("ssi3_ipg",      "ipg",               base + 0x7c, 22);