arm64/esr: Add decode of ISS2 to data abort reporting

The architecture has added more information about faults to ISS2 within
ESR. Add decode of this to our data abort fault decode to aid diagnostics.
Features that are not currently enabled are included here for completeness.

Since the architecture specifies the values of bits within ISS2 in terms
of ISS2 rather than in terms of the register as a whole we do so for our
definitions as well, this makes it easier to review bitfield definitions.

Signed-off-by: Mark Brown <broonie@kernel.org>
Link: https://lore.kernel.org/r/20230417-arm64-iss2-dabt-decode-v3-2-c1fa503e503a@kernel.org
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>

diff --git a/arch/arm64/include/asm/esr.h b/arch/arm64/include/asm/esr.h
index 0bd879007168a759a1dc821c4464dd6f6184c3d5..0552a29f026b267ddb1962f6ae81e4155673f249 100644 (file)
--- a/arch/arm64/include/asm/esr.h
+++ b/arch/arm64/include/asm/esr.h
@@ -77,6 +77,9 @@
 #define ESR_ELx_IL             (UL(1) << ESR_ELx_IL_SHIFT)
 #define ESR_ELx_ISS_MASK       (GENMASK(24, 0))
 #define ESR_ELx_ISS(esr)       ((esr) & ESR_ELx_ISS_MASK)
+#define ESR_ELx_ISS2_SHIFT     (32)
+#define ESR_ELx_ISS2_MASK      (GENMASK_ULL(55, 32))
+#define ESR_ELx_ISS2(esr)      (((esr) & ESR_ELx_ISS2_MASK) >> ESR_ELx_ISS2_SHIFT)
 
 /* ISS field definitions shared by different classes */
 #define ESR_ELx_WNR_SHIFT      (6)
@@ -140,6 +143,20 @@
 #define ESR_ELx_CM_SHIFT       (8)
 #define ESR_ELx_CM             (UL(1) << ESR_ELx_CM_SHIFT)
 
+/* ISS2 field definitions for Data Aborts */
+#define ESR_ELx_TnD_SHIFT      (10)
+#define ESR_ELx_TnD            (UL(1) << ESR_ELx_TnD_SHIFT)
+#define ESR_ELx_TagAccess_SHIFT        (9)
+#define ESR_ELx_TagAccess      (UL(1) << ESR_ELx_TagAccess_SHIFT)
+#define ESR_ELx_GCS_SHIFT      (8)
+#define ESR_ELx_GCS            (UL(1) << ESR_ELx_GCS_SHIFT)
+#define ESR_ELx_Overlay_SHIFT  (6)
+#define ESR_ELx_Overlay                (UL(1) << ESR_ELx_Overlay_SHIFT)
+#define ESR_ELx_DirtyBit_SHIFT (5)
+#define ESR_ELx_DirtyBit       (UL(1) << ESR_ELx_DirtyBit_SHIFT)
+#define ESR_ELx_Xs_SHIFT       (0)
+#define ESR_ELx_Xs_MASK                (GENMASK_ULL(4, 0))
+
 /* ISS field definitions for exceptions taken in to Hyp */
 #define ESR_ELx_CV             (UL(1) << 24)
 #define ESR_ELx_COND_SHIFT     (20)

diff --git a/arch/arm64/mm/fault.c b/arch/arm64/mm/fault.c
index cb21ccd7940d0e3cd9b496fa1c3110b3cfb1f75e..fb5e0fb8b2a74b101849d2478fa3487589f2ff39 100644 (file)
--- a/arch/arm64/mm/fault.c
+++ b/arch/arm64/mm/fault.c
@@ -66,6 +66,8 @@ static inline const struct fault_info *esr_to_debug_fault_info(unsigned long esr
 
 static void data_abort_decode(unsigned long esr)
 {
+       unsigned long iss2 = ESR_ELx_ISS2(esr);
+
        pr_alert("Data abort info:\n");
 
        if (esr & ESR_ELx_ISV) {
@@ -78,12 +80,21 @@ static void data_abort_decode(unsigned long esr)
                         (esr & ESR_ELx_SF) >> ESR_ELx_SF_SHIFT,
                         (esr & ESR_ELx_AR) >> ESR_ELx_AR_SHIFT);
        } else {
-               pr_alert("  ISV = 0, ISS = 0x%08lx\n", esr & ESR_ELx_ISS_MASK);
+               pr_alert("  ISV = 0, ISS = 0x%08lx, ISS2 = 0x%08lx\n",
+                        esr & ESR_ELx_ISS_MASK, iss2);
        }
 
-       pr_alert("  CM = %lu, WnR = %lu\n",
+       pr_alert("  CM = %lu, WnR = %lu, TnD = %lu, TagAccess = %lu\n",
                 (esr & ESR_ELx_CM) >> ESR_ELx_CM_SHIFT,
-                (esr & ESR_ELx_WNR) >> ESR_ELx_WNR_SHIFT);
+                (esr & ESR_ELx_WNR) >> ESR_ELx_WNR_SHIFT,
+                (iss2 & ESR_ELx_TnD) >> ESR_ELx_TnD_SHIFT,
+                (iss2 & ESR_ELx_TagAccess) >> ESR_ELx_TagAccess_SHIFT);
+
+       pr_alert("  GCS = %ld, Overlay = %lu, DirtyBit = %lu, Xs = %llu\n",
+                (iss2 & ESR_ELx_GCS) >> ESR_ELx_GCS_SHIFT,
+                (iss2 & ESR_ELx_Overlay) >> ESR_ELx_Overlay_SHIFT,
+                (iss2 & ESR_ELx_DirtyBit) >> ESR_ELx_DirtyBit_SHIFT,
+                (iss2 & ESR_ELx_Xs_MASK) >> ESR_ELx_Xs_SHIFT);
 }
 
 static void mem_abort_decode(unsigned long esr)