net: ethernet: oa_tc6: implement software reset

Reset complete bit is set when the MAC-PHY reset completes and ready for
configuration. Additionally reset complete bit in the STS0 register has
to be written by one upon reset complete to clear the interrupt.

Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: Parthiban Veerasooran <Parthiban.Veerasooran@microchip.com>
Link: https://patch.msgid.link/20240909082514.262942-5-Parthiban.Veerasooran@microchip.com
Signed-off-by: Jakub Kicinski <kuba@kernel.org>

diff --git a/drivers/net/ethernet/oa_tc6.c b/drivers/net/ethernet/oa_tc6.c
index 72bab923443613aebbcdb8068fd0248980f36b2b..f774ed397213c9660e7079cb04d633201ad2e4f6 100644 (file)
--- a/drivers/net/ethernet/oa_tc6.c
+++ b/drivers/net/ethernet/oa_tc6.c
@@ -6,8 +6,18 @@
  */
 
 #include <linux/bitfield.h>
+#include <linux/iopoll.h>
 #include <linux/oa_tc6.h>
 
+/* OPEN Alliance TC6 registers */
+/* Reset Control and Status Register */
+#define OA_TC6_REG_RESET                       0x0003
+#define RESET_SWRESET                          BIT(0)  /* Software Reset */
+
+/* Status Register #0 */
+#define OA_TC6_REG_STATUS0                     0x0008
+#define STATUS0_RESETC                         BIT(6)  /* Reset Complete */
+
 /* Control command header */
 #define OA_TC6_CTRL_HEADER_DATA_NOT_CTRL       BIT(31)
 #define OA_TC6_CTRL_HEADER_WRITE_NOT_READ      BIT(29)
@@ -24,6 +34,8 @@
                                                (OA_TC6_CTRL_MAX_REGISTERS *\
                                                OA_TC6_CTRL_REG_VALUE_SIZE) +\
                                                OA_TC6_CTRL_IGNORED_SIZE)
+#define STATUS0_RESETC_POLL_DELAY              1000
+#define STATUS0_RESETC_POLL_TIMEOUT            1000000
 
 /* Internal structure for MAC-PHY drivers */
 struct oa_tc6 {
@@ -279,6 +291,42 @@ int oa_tc6_write_register(struct oa_tc6 *tc6, u32 address, u32 value)
 }
 EXPORT_SYMBOL_GPL(oa_tc6_write_register);
 
+static int oa_tc6_read_status0(struct oa_tc6 *tc6)
+{
+       u32 regval;
+       int ret;
+
+       ret = oa_tc6_read_register(tc6, OA_TC6_REG_STATUS0, &regval);
+       if (ret) {
+               dev_err(&tc6->spi->dev, "STATUS0 register read failed: %d\n",
+                       ret);
+               return 0;
+       }
+
+       return regval;
+}
+
+static int oa_tc6_sw_reset_macphy(struct oa_tc6 *tc6)
+{
+       u32 regval = RESET_SWRESET;
+       int ret;
+
+       ret = oa_tc6_write_register(tc6, OA_TC6_REG_RESET, regval);
+       if (ret)
+               return ret;
+
+       /* Poll for soft reset complete for every 1ms until 1s timeout */
+       ret = readx_poll_timeout(oa_tc6_read_status0, tc6, regval,
+                                regval & STATUS0_RESETC,
+                                STATUS0_RESETC_POLL_DELAY,
+                                STATUS0_RESETC_POLL_TIMEOUT);
+       if (ret)
+               return -ENODEV;
+
+       /* Clear the reset complete status */
+       return oa_tc6_write_register(tc6, OA_TC6_REG_STATUS0, regval);
+}
+
 /**
  * oa_tc6_init - allocates and initializes oa_tc6 structure.
  * @spi: device with which data will be exchanged.
@@ -289,6 +337,7 @@ EXPORT_SYMBOL_GPL(oa_tc6_write_register);
 struct oa_tc6 *oa_tc6_init(struct spi_device *spi)
 {
        struct oa_tc6 *tc6;
+       int ret;
 
        tc6 = devm_kzalloc(&spi->dev, sizeof(*tc6), GFP_KERNEL);
        if (!tc6)
@@ -313,6 +362,13 @@ struct oa_tc6 *oa_tc6_init(struct spi_device *spi)
        if (!tc6->spi_ctrl_rx_buf)
                return NULL;
 
+       ret = oa_tc6_sw_reset_macphy(tc6);
+       if (ret) {
+               dev_err(&tc6->spi->dev,
+                       "MAC-PHY software reset failed: %d\n", ret);
+               return NULL;
+       }
+
        return tc6;
 }
 EXPORT_SYMBOL_GPL(oa_tc6_init);