clk: meson: mpll: fix mpll0 fractional part ignored

mpll0 clock is special compared to the other mplls. It needs another
bit (ssen) to be set to activate the fractional part the mpll divider

Fixes: 007e6e5c5f01 ("clk: meson: mpll: add rw operation")
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>

diff --git a/drivers/clk/meson/clk-mpll.c b/drivers/clk/meson/clk-mpll.c
index 39eab69fe51a8a76791029ae718c575f16843630..44a5a535ca6334ebe17acf74ca38fea45ab86708 100644 (file)
--- a/drivers/clk/meson/clk-mpll.c
+++ b/drivers/clk/meson/clk-mpll.c
@@ -161,6 +161,13 @@ static int mpll_set_rate(struct clk_hw *hw,
        reg = PARM_SET(p->width, p->shift, reg, 1);
        writel(reg, mpll->base + p->reg_off);
 
+       p = &mpll->ssen;
+       if (p->width != 0) {
+               reg = readl(mpll->base + p->reg_off);
+               reg = PARM_SET(p->width, p->shift, reg, 1);
+               writel(reg, mpll->base + p->reg_off);
+       }
+
        p = &mpll->n2;
        reg = readl(mpll->base + p->reg_off);
        reg = PARM_SET(p->width, p->shift, reg, n2);

diff --git a/drivers/clk/meson/clkc.h b/drivers/clk/meson/clkc.h
index d6feafe8bd6cea9ff9d61b0416f7c5d7858a044a..1629da9b414195c5159ee96449f5e5a22dec39c6 100644 (file)
--- a/drivers/clk/meson/clkc.h
+++ b/drivers/clk/meson/clkc.h
@@ -118,6 +118,7 @@ struct meson_clk_mpll {
        struct parm sdm_en;
        struct parm n2;
        struct parm en;
+       struct parm ssen;
        spinlock_t *lock;
 };
 

diff --git a/drivers/clk/meson/gxbb.c b/drivers/clk/meson/gxbb.c
index a897ea45327c985b189e9c5e81ac40028a682d7d..a7ea5f3da89d5357c2332f8a7fe4afa609cb9997 100644 (file)
--- a/drivers/clk/meson/gxbb.c
+++ b/drivers/clk/meson/gxbb.c
@@ -528,6 +528,11 @@ static struct meson_clk_mpll gxbb_mpll0 = {
                .shift   = 14,
                .width   = 1,
        },
+       .ssen = {
+               .reg_off = HHI_MPLL_CNTL,
+               .shift   = 25,
+               .width   = 1,
+       },
        .lock = &clk_lock,
        .hw.init = &(struct clk_init_data){
                .name = "mpll0",

diff --git a/drivers/clk/meson/meson8b.c b/drivers/clk/meson/meson8b.c
index bb3f1de876b1a8cd6bd5f191c6f2ff0737751aa7..6ec512ad259805c34b57be3ee96eddef149599ee 100644 (file)
--- a/drivers/clk/meson/meson8b.c
+++ b/drivers/clk/meson/meson8b.c
@@ -267,6 +267,11 @@ static struct meson_clk_mpll meson8b_mpll0 = {
                .shift   = 14,
                .width   = 1,
        },
+       .ssen = {
+               .reg_off = HHI_MPLL_CNTL,
+               .shift   = 25,
+               .width   = 1,
+       },
        .lock = &clk_lock,
        .hw.init = &(struct clk_init_data){
                .name = "mpll0",